iucode-tool: update UPSTREAM_CHECK_URI

Update UPSTREAM_CHECK_URI to check the correct latest stable
verison.

Before the patch:
$ devtool latest-version iucode-tool
INFO: Current version: 2.3.1
INFO: Latest version:

After the patch:
$ devtool latest-version iucode-tool
INFO: Current version: 2.3.1
INFO: Latest version: 2.3.1

Signed-off-by: Yi Zhao <yi.zhao@windriver.com>
Signed-off-by: Yogesh Tyagi <yogesh.tyagi@intel.com>

CHANGELOG

@@ -1,87 +0,0 @@
-This file will only list major changes that occur within a release.
-For a full list of changes, view the git log of the repository.
-
-Rocko Release 11/2017
-=====================
-
-Moved qat support to separate layer
------------------------------------
-Quick Assist Technology (QAT) is more middleware and should not be part of the
-core BSP. The new layer can be found here:
-https://git.yoctoproject.org/cgit/cgit.cgi/meta-intel-qat/
-
-Moved dpdk support to separate layer
-------------------------------------
-We had some requests to make DPDK standalone so that it could be included
-without bringing in anything else from meta-intel, as it is not specific to
-Intel(R) hardware. The new layer is located here:
-https://git.yoctoproject.org/cgit/cgit.cgi/meta-dpdk/
-
-Added support for out-of-tree iwlwifi drivers
----------------------------------------------
-Backport-iwlwifi out-of-tree wifi modules are now available via meta-intel.
-Backport-iwlwifi brings the latest iwlwifi drivers to almost any kernel
-Note that mac80211 and cfg80211 backports are also necessary, which will most
-likely cause incompatibility with other in-tree wifi drivers.
-See https://wireless.wiki.kernel.org/en/users/drivers/iwlwifi for more info.
-
-Added support for out-of-tree ixgbe drivers
--------------------------------------------
-The out-of-tree ixgbe drivers bring ixgbe support to nearly any kernel. See
-here: http://www.intel.com/network/connectivity/products/server_adapters.htm
-
-Added an implementation of Secure Boot
---------------------------------------
-meta-intel now supports a simple Secure Boot implementation. This implementation
-consists of a single binary consisting of an EFI stub, the kernel, an
-initrd, and a kernel command line. The binary is then signed via keys defined by
-the variables SECUREBOOT_SIGNING_KEY and SECUREBOOT_SIGNING_CERT. These keys
-should match the keys embedded in your hardware's firmware.
-See documentation/secureboot/README for more information on this feature.
-
-Improved Yocto Project Compatibility status
--------------------------------------------
-The common layer should now be considered Yocto Project compatible - it should
-no longer modify OE-core values when adding the layer to your bblayers.conf.
-The meta-tlk layer is still not Yocto Project compatible, however.
-
-Pyro Release 5/2017
-===================
-
-Changed default kernel provider from linux-yocto to linux-intel.
-----------------------------------------------------------------
-Linux-intel is an Intel(R)-maintained kernel based on the latest stable
-branch, along with backports from upstream to better support Intel(R)
-hardware. The intel-linux kernel also has a branch with the preempt-rt
-patches applied, providing a preempt-rt kernel with no additional work.
-
-Added QEMU support.
--------------------
-We now build several virtio drivers into the kernel by default, and
-have qemuboot.conf files for intel-corei7-64 and intel-core2-32
-targets. This allows one to do basic testing on meta-intel images
-without having to use hardware. The virtio drivers are added via
-KERNEL_FEATURES_INTEL_COMMON. This prevents them from being added to
-custom kernels by default. They can be removed by adding the
-following to a conf or kernel bbappend file:
-  KERNEL_FEATURES_INTEL_COMMON:remove = “cfg/virtio.scc”
-OVMF firmware is also built and can be used in order to emulate a UEFI
-environment. A full runqemu command line for intel-corei7-64 could look
-like this:
-  runqemu core-image-minimal intel-corei7-64 wic ovmf
-
-Musl support
-------------
-Meta-intel is now compatible with the musl C library. You can specify musl
-As your C library by adding the following to your local.conf:
-  TCLIBC = “musl”
-Note: there is a known failure with DPDK.
-
-X32 support
------------
-The meta-intel layer can now build with the x32 tune settings in a multi-lib
-setting, it will not work in as the primary MACHINE tune as the bootloader needs
-to be built as a 64bit binary. The setup for this would be as follows:
-  require conf/multilib.conf
-  MULTILIBS = "multilib:libx32
-  DEFAULTTUNE:virtclass-multilib-libx32 = "corei7-64-x32"

MAINTAINERS

@@ -1,32 +0,0 @@
-This file contains a list of BSP maintainers for the BSPs contained in
-the meta-intel repository.
-
-The purpose of this file is to provide contact information for
-specific BSPs and other code contained within meta-intel.  You should
-address questions and patches for a particular BSP or other code to
-the appropriate maintainer listed in this file, cc'ing the meta-intel
-mailing list.  This ensures that your question or patch will be
-addressed by the appropriate person, and that it will be seen by other
-users who may be facing similar problems or questions.
-
-Please see the top-level README file for guidelines relating to the
-details of submitting patches, reporting problems, or asking questions
-about any of the BSPs or other recipes contained within meta-intel.
-
-Descriptions of section entries:
-
-	M: Mail patches to: FullName <address@domain>
-	F: Files and directories with wildcard patterns.
-	   A trailing slash includes all files and subdirectory files.
-	   F:	common/	 all files in and below common
-	   F:	common/* all files in common, but not below
-	   One pattern per line.  Multiple F: lines acceptable.
-
-Please keep this list in alphabetical order.
-
-Maintainers List (try to look for most precise areas first)
-
-		-----------------------------------
-
-M:	Anuj Mittal <anuj.mittal@intel.com>
-F:	*

README

@@ -1,459 +0,0 @@
-meta-intel
-==========
-
-This README file contains information on building and booting
-meta-intel BSP layers.  Please see the corresponding sections below
-for details.
-
-
-Yocto Project Compatible
-========================
-
-The BSPs contained in this layer are compatible with the Yocto Project
-as per the requirements listed here:
-
-  https://www.yoctoproject.org/webform/yocto-project-compatible-registration
-
-
-Dependencies
-============
-
-This layer depends on:
-
-  URI: git://git.openembedded.org/bitbake
-
-  URI: git://git.openembedded.org/openembedded-core
-  layers: meta
-  branch: master
-
-
-Table of Contents
-=================
-
-  I. Overview
-  II. Building and booting meta-intel BSP layers
-     a. Building the intel-common BSP layers
-     b. Booting the intel-common BSP images
-     c. Building the installer image
-  III. Technical Miscellany
-     Benefits of using meta-intel
-     The intel-common kernel package architecture
-     Intel-specific machine features
-  IV. Tested Hardware
-  V.  Guidelines for submitting patches
-
-
-I. Overview
-===========
-
-This is the location for Intel-maintained BSPs.
-
-For details on the intel-common, see the information below.
-
-For all others, please see the README files contained in the
-individual BSP layers for BSP-specific information.
-
-If you have problems with or questions about a particular BSP, please
-contact the maintainer listed in the MAINTAINERS file directly (cc:ing
-the Yocto mailing list puts it in the archive and helps other people
-who might have the same questions in the future), but please try to do
-the following first:
-
-  - look in the Yocto Project Bugzilla
-    (http://bugzilla.yoctoproject.org/) to see if a problem has
-    already been reported
-
-  - look through recent entries of the meta-intel
-    (https://lists.yoctoproject.org/pipermail/meta-intel/) and Yocto
-    (https://lists.yoctoproject.org/pipermail/yocto/) mailing list
-    archives to see if other people have run into similar problems or
-    had similar questions answered.
-
-If you believe you have encountered a bug, you can open a new bug and
-enter the details in the Yocto Project Bugzilla
-(http://bugzilla.yoctoproject.org/).  If you're relatively certain
-that it's a bug against the BSP itself, please use the 'Yocto Project
-Components: BSPs | meta-intel' category for the bug; otherwise, please
-submit the bug against the most likely category for the problem - if
-you're wrong, it's not a big deal and the bug will be recategorized
-upon triage.
-
-
-II. Building and booting meta-intel BSP layers
-==============================================
-
-The following sections contain information on building and booting the
-BSPs contained in the meta-intel layer.
-
-Note that these instructions specifically cover the intel-common, which
-may or may not be applicable to other BSPs contained in this layer - if
-a given BSP contains its own README, that version should be used instead,
-and these instructions can be ignored.
-
-a. Building the intel-common BSP layers
--------------------------------------------------
-
-In order to build an image with BSP support for a given release, you
-need to download the corresponding BSP tarball from the 'Board Support
-Package (BSP) Downloads' page of the Yocto Project website (or
-equivalently, check out the appropriate branch from the meta-intel git
-repository, see below).  For the intel-common BSPs, those tarballs would
-correspond to the following choices in the BSP downloads section:
-
- - Intel-core2-32 Intel® Common Core BSP (Intel-core2-32)
- - Intel-corei7-64 Intel® Common Core BSP (Intel-corei7-64)
-
-The intel-* BSPs, also known as the intel-common BSPs, provide a few
-carefully selected tune options and generic hardware support to cover
-the majority of current Intel CPUs and devices. The naming follows the
-convention of intel-<TUNE>-<BITS>, where TUNE is the gcc cpu-type
-(used with mtune and march typically) and BITS is either 32 bit or 64
-bit.
-
-Having done that, and assuming you extracted the BSP tarball contents
-at the top-level of your yocto build tree, you can build a BSP image
-by adding the location of the meta-intel layer to bblayers.conf e.g.:
-
-  yocto/meta-intel \
-
-To enable a particular machine, you need to add a MACHINE line naming
-the BSP to the local.conf file:
-
-  MACHINE ?= "xxx"
-
-where 'xxx' is replaced by one of the following BSP names:
-
- - intel-core2-32
-
-   This BSP is optimized for the Core2 family of CPUs as well as all
-   Atom CPUs prior to the Silvermont core.
-
- - intel-corei7-64
-
-   This BSP is optimized for Nehalem and later Core and Xeon CPUs as
-   well as Silvermont and later Atom CPUs, such as the Baytrail SoCs.
-
-You should then be able to build an image as such:
-
-  $ source oe-init-build-env
-  $ bitbake core-image-sato
-
-At the end of a successful build, you should have an image that
-you can boot from a USB flash drive (see instructions on how to do
-that below, in the section 'Booting the intel-common BSP images').
-
-As an alternative to downloading the BSP tarball, you can also work
-directly from the meta-intel git repository.  For each BSP in the
-'meta-intel' repository, there are multiple branches, one
-corresponding to each major release starting with 'laverne' (0.90), in
-addition to the latest code which tracks the current master (note that
-not all BSPs are present in every release).  Instead of extracting
-a BSP tarball at the top level of your yocto build tree, you can
-equivalently check out the appropriate branch from the meta-intel
-repository at the same location.
-
-b. Booting the intel-common BSP images
---------------------------------------
-
-If you've built your own image, either from the downloaded BSP layer
-or from the meta-intel git repository, you'll find the bootable
-image in the build/tmp/deploy/images/xxx directory, where again
-'xxx' refers to the machine name used in the build.
-
-Under Linux, insert a USB flash drive.  Assuming the USB flash drive
-takes device /dev/sdf, use dd to copy the image to it.  Before the image
-can be burned onto a USB drive, it should be un-mounted. Some Linux distros
-may automatically mount a USB drive when it is plugged in. Using USB device
-/dev/sdf as an example, find all mounted partitions:
-
-    $ mount | grep sdf
-
-and un-mount those that are mounted, for example:
-
-    $ umount /dev/sdf1
-    $ umount /dev/sdf2
-
-Now burn the image onto the USB drive:
-
-    $ sudo dd if=core-image-sato-intel-corei7-64.wic of=/dev/sdf status=progress
-    $ sync
-    $ eject /dev/sdf
-
-This should give you a bootable USB flash device.  Insert the device
-into a bootable USB socket on the target, and power on.  This should
-result in a system booted to the Sato graphical desktop.
-
-If you want a terminal, use the arrows at the top of the UI to move to
-different pages of available applications, one of which is named
-'Terminal'.  Clicking that should give you a root terminal.
-
-If you want to ssh into the system, you can use the root terminal to
-ifconfig the IP address and use that to ssh in.  The root password is
-empty, so to log in type 'root' for the user name and hit 'Enter' at
-the Password prompt: and you should be in.
-
-If you find you're getting corrupt images on the USB (it doesn't show
-the syslinux boot: prompt, or the boot: prompt contains strange
-characters), try doing this first:
-
-    $ dd if=/dev/zero of=/dev/sdf bs=1M count=512
-
-c. Building the installer image
------------------------------------------------
-
-If you plan to install your image to your target machine, you can build a wic
-based installer image instead of default wic image. To build it, you need to
-add below configuration to local.conf :
-
-  WKS_FILE = "image-installer.wks.in"
-  IMAGE_FSTYPES:append = " ext4"
-  IMAGE_TYPEDEP_wic = "ext4"
-  INITRD_IMAGE_LIVE="core-image-minimal-initramfs"
-  do_image_wic[depends] += "${INITRD_IMAGE_LIVE}:do_image_complete"
-  do_rootfs[depends] += "virtual/kernel:do_deploy"
-  IMAGE_BOOT_FILES:append = "\
-      ${KERNEL_IMAGETYPE} \
-      microcode.cpio \
-      ${IMGDEPLOYDIR}/${IMAGE_BASENAME}-${MACHINE}.ext4;rootfs.img \
-      ${@bb.utils.contains('EFI_PROVIDER', 'grub-efi', 'grub-efi-bootx64.efi;EFI/BOOT/bootx64.efi', '', d)} \
-      ${@bb.utils.contains('EFI_PROVIDER', 'grub-efi', '${IMAGE_ROOTFS}/boot/EFI/BOOT/grub.cfg;EFI/BOOT/grub.cfg', '', d)} \
-      ${@bb.utils.contains('EFI_PROVIDER', 'systemd-boot', 'systemd-bootx64.efi;EFI/BOOT/bootx64.efi', '', d)} \
-      ${@bb.utils.contains('EFI_PROVIDER', 'systemd-boot', '${IMAGE_ROOTFS}/boot/loader/loader.conf;loader/loader.conf ', '', d)} \
-      ${@bb.utils.contains('EFI_PROVIDER', 'systemd-boot', '${IMAGE_ROOTFS}/boot/loader/entries/boot.conf;loader/entries/boot.conf', '', d)} "
-
-Burn the wic image onto USB flash device, insert the device to target machine
-and power on. This should start the installation process.
-
-III. Technical Miscellany
-=========================
-
-Benefits of using meta-intel
-----------------------------
-
-Using meta-intel has the following benefits over a generic BSP:
-
-tune flags
-++++++++++
-intel-* MACHINEs each have different compilation flags appropriate for their
-targeted hardware sets. intel-corei7-64 has tune flags appropriate for modern
-64-bit Intel Core i microarchitecture, and includes instruction sets up to
-SSE4.2. intel-core2-32 has tune flags appropriate for legacy 32-bit Intel Core2
-microarchitecture, and includes instruction sets up to SSE3.
-
-linux-intel kernel
-++++++++++++++++++
-The linux-intel kernel is an initiative to bring better Intel(R) hardware
-support to the current LTS linux kernel. It contains a base LTS kernel with
-additional backports from upstream Intel drivers. In addition, a default kernel
-config containing most features found on Intel boards is supplied via the
-yocto-kernel-cache.
-
-graphics stack
-++++++++++++++
-Meta-intel provides the latest Intel Graphics Linux Stack drivers to support
-Intel hardware as defined by the https://01.org/linuxgraphics.
-
-Other software
-++++++++++++++
-  * intel ucode - provides the latest microcode updates for Intel processors
-
-  * thermald - which proactively controls thermal, using P-states, T-states, and
-the Intel power clamp driver.
-(https://01.org/linux-thermal-daemon/documentation/introduction-thermal-daemon)
-
-The intel-common kernel package architecture
---------------------------------------------
-
-These BSPs use what we call the intel-common Linux kernel package
-architecture. This includes core2-32-intel-common and
-corei7-64-intel-common. These kernel packages can also be used by any
-of the BSPs in meta-intel that choose to include the
-intel-common-pkgarch.inc file.
-
-To minimize the proliferation of vendor trees, reduce the sources we
-must support, and consolidate QA efforts, all BSP maintainers are
-encouraged to make use of the intel-common Linux kernel package
-architecture.
-
-Intel-specific machine features
--------------------------------
-
-The meta-intel layer makes some additional machine features available
-to BSPs.  These machine features can be used in a BSP layer in the
-same way that machine features are used in other layers based on
-oe-core, via the MACHINE_FEATURES variable.
-
-Requirements
-++++++++++++
-
-The meta-intel-specific machine features are only available to a BSP
-when the meta-intel layer is included in the build configuration, and
-the meta-intel.inc file is included in the machine configuration of
-that BSP.
-
-To make these features available for your machine, you will need to:
-
-  1. include a configuration line such as the below in bblayers.conf
-       BBLAYERS += "<local path>/meta-intel"
-  2. include the following line in the machine configuration file
-       require conf/machine/include/meta-intel.inc
-
-Once the above requirements are met, the machine features provided by
-the meta-intel layer will be available for the BSP to use.
-
-Available machine features
-++++++++++++++++++++++++++
-
-Currently, the meta-intel layer makes the following set of
-Intel-specific machine features available:
-
-  * intel-ucode
-
-These machine features can be included by listing them in the
-MACHINE_FEATURES variable in the machine configuration file.  For
-example:
-
-    MACHINE_FEATURES += "intel-ucode"
-
-Machine feature details
-+++++++++++++++++++++++
-
- * intel-ucode
-
-    This feature provides support for microcode updates to Intel
-    processors.  The intel-ucode feature runs at early boot and uses
-    the microcode data file added by the feature into the BSP's
-    initrd.  It also puts the userland microcode-updating tool,
-    iucode_tool, into the target images along with the microcode data
-    file.
-
-    Q. Why might a user want to enable the intel-ucode feature?
-
-    A. Intel releases microcode updates to correct processor behavior
-       as documented in the respective processor specification
-       updates.  While the normal approach to getting such microcode
-       updates is via a BIOS upgrade, this can be an administrative
-       hassle and not always possible in the field.  The intel-ucode
-       feature enables the microcode update capability present in the
-       Linux kernel.  It provides an easy path for upgrading processor
-       microcode without the need to change the BIOS.  If the feature
-       is enabled, it is also possible to update the existing target
-       images with a newer microcode update in the future.
-
-    Q. How would a user bundle only target-specific microcode in the
-       target image?
-
-    A. The Intel microcode data file released by Intel contains
-       microcode updates for multiple processors.  If the BSP image is
-       meant to run on only a certain subset of processor types, a
-       processor-specific subset of microcode can be bundled into the
-       target image via the UCODE_FILTER_PARAMETERS variable.  This
-       works by listing a sequence of iucode-tool parameters in the
-       UCODE_FILTER_PARAMETERS variable, which in this case will
-       select only the specific microcode relevant to the BSP.  For
-       more information on the underlying parameters refer to the
-       iucode-tool manual page at http://manned.org/iucode-tool
-
-       To define a set of parameters for microcode-filtering via the
-       UCODE_FILTER_PARAMETERS variable, one needs to identify the
-       cpuid signatures of all the processors the BSP is meant to run
-       on.  One way to determine the cpuid signature for a specific
-       processor is to build and run an intel-ucode-feature-enabled
-       image on the target hardware, without first assigning any value
-       to the UCODE_FILTER_PARAMETERS variable, and then once the
-       image is booted, run the "ucode_tool -S" command to have the
-       ucode tool scan the system for processor signatures.  These
-       signatures can then be used in the UCODE_FILTER_PARAMETERS
-       variable in conjunction with -s parameter.  For example, for
-       the fri2 BSP, the cpuid can be determined as such:
-
-         [root@fri2 ~]# iucode_tool -S
-         iucode_tool: system has processor(s) with signature 0x00020661
-
-       Given that output, a suitable UCODE_FILTER_PARAMETERS variable
-       definition could be specified in the machine configuration as
-       such:
-
-         UCODE_FILTER_PARAMETERS = "-s 0x00020661"
-
-    Q. Are there any reasons a user might want to disable the
-       intel-ucode feature?
-
-    A. The microcode data file and associated tools occupy a small
-       amount of space (a few KB) on the target image.  BSPs which are
-       highly sensitive to target image size and which are not
-       experiencing microcode-related issues might consider not
-       enabling this feature.
-
-
-IV. Tested Hardware
-===================
-
-The following undergo regular basic testing with their respective MACHINE types.
-Note that both 64-bit and 32-bit firmware is available for the MinnowBoard
-Turbot, so it is tested against both intel-corei7-64 and intel-core2-32.
-
-intel-corei7-64:
-    NUC6i5SYH
-    NUC7i7BNH
-    Coffee Lake-H
-
-intel-core2-32:
-    MinnowBoard Turbot
-
-
-V. Guidelines for submitting patches
-====================================
-
-Please submit any patches against meta-intel BSPs to the meta-intel
-mailing list (meta-intel@lists.yoctoproject.org).  Also, if your patches are
-available via a public git repository, please also include a URL to
-the repo and branch containing your patches as that makes it easier
-for maintainers to grab and test your patches.
-
-There are patch submission scripts available that will, among other
-things, automatically include the repo URL and branch as mentioned.
-Please see the Yocto Project Development Manual sections entitled
-'Using Scripts to Push a Change Upstream and Request a Pull' and
-'Using Email to Submit a Patch' for details.
-
-Regardless of how you submit a patch or patchset, the patches should
-at minimum follow the suggestions outlined in the 'Submitting a Change
-to the Yocto Project' section in the Yocto Project Development Manual.
-Specifically, they should:
-
-  - Include a 'Signed-off-by:' line.  A commit can't legally be pulled
-    in without this.
-
-  - Provide a single-line, short summary of the change.  This short
-    description should be prefixed by the BSP or recipe name, as
-    appropriate, followed by a colon.  Capitalize the first character
-    of the summary (following the colon).
-
-  - For the body of the commit message, provide detailed information
-    that describes what you changed, why you made the change, and the
-    approach you used.
-
-  - If the change addresses a specific bug or issue that is associated
-    with a bug-tracking ID, include a reference to that ID in your
-    detailed description in the following format: [YOCTO #<bug-id>].
-
-  - Pay attention to line length - please don't allow any particular
-    line in the commit message to stretch past 72 characters.
-
-  - For any non-trivial patch, provide information about how you
-    tested the patch, and for any non-trivial or non-obvious testing
-    setup, provide details of that setup.
-
-Doing a quick 'git log' in meta-intel will provide you with many
-examples of good example commits if you have questions about any
-aspect of the preferred format.
-
-The meta-intel maintainers will do their best to review and/or pull in
-a patch or patchset within 24 hours of the time it was posted.  For
-larger and/or more involved patches and patchsets, the review process
-may take longer.
-
-Please see the meta-intel/MAINTAINERS file for the list of maintainers
-and their specific areas; it's also a good idea to cc: the specific
-maintainer, if applicable.

README.md

@@ -0,0 +1,35 @@
+# meta-intel
+
+OpenEmbedded/Yocto BSP layer for Intel platforms.
+
+## Dependencies
+
+This layer primarily depends on OpenEmbedded-Core (OE-Core). However, certain
+recipes may require additional layers to support optional features or
+programming languages not supported by OE-Core. Such recipes are located within
+the `dynamic-layers` directory.
+
+Base dependencies:
+- [Bitbake](https://git.openembedded.org/bitbake)
+- [OE-Core](https://git.openembedded.org/openembedded-core)
+
+Dynamic additional dependencies:
+
+- [meta-openembedded](https://git.openembedded.org/meta-openembedded/tree/meta-oe)
+- [meta-python](https://git.openembedded.org/meta-openembedded/tree/meta-python)
+- [meta-clang](https://github.com/kraj/meta-clang.git)
+
+
+## Contents
+
+- [Building and booting meta-intel BSP layers](documentation/building_and_booting.md)
+- [Intel oneAPI DPC++/C++ Compiler](documentation/dpcpp-compiler.md)
+- [Build Image with OpenVINO™ toolkit](documentation/openvino.md)
+- [Tested Hardware](documentation/tested_hardware.md)
+- [Guidelines for submitting patches](documentation/submitting_patches.md)
+- [Reporting bugs](documentation/reporting_bugs.md)
+- [Reporting security bugs](SECURITY.md)
+
+## Maintainers
+
+- Yogesh Tyagi <yogesh.tyagi@intel.com>

README.sources

@@ -1,17 +0,0 @@
-The sources for the packages comprising the images shipped with this
-BSP can be found at the following location:
-
-http://downloads.yoctoproject.org/mirror/sources/
-
-The metadata used to generate the images shipped with this BSP, in
-addition to the code contained in this BSP, can be found at the
-following location:
-
-http://downloads.yoctoproject.org/releases/yocto/yocto-2.7/poky-warrior-21.0.0.tar.bz2
-
-The metadata used to generate the images shipped with this BSP, in
-addition to the code contained in this BSP, can also be found at the
-following locations:
-
-git://git.yoctoproject.org/poky.git
-git://git.yoctoproject.org/meta-intel

SECURITY.md

@@ -0,0 +1,6 @@
+# Security Policy
+Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation.
+
+## Reporting a Vulnerability
+Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html).
+

classes/uefi-comboapp.bbclass

@@ -1,151 +0,0 @@
-# This class brings a more generic version of the UEFI combo app from refkit to meta-intel.
-# It uses a combo file, containing kernel, initramfs and
-# command line, presented to the BIOS as UEFI application, by prepending
-# it with the efi stub obtained from systemd-boot.
-
-# Don't add syslinux or build an ISO
-PCBIOS:forcevariable = "0"
-NOISO:forcevariable  = "1"
-
-# image-live.bbclass will default INITRD_LIVE to the image INITRD_IMAGE creates.
-# We want behavior to be consistent whether or not "live" is in IMAGE_FSTYPES, so
-# we default INITRD_LIVE to the INITRD_IMAGE as well.
-INITRD_IMAGE ?= "core-image-minimal-initramfs"
-INITRD_LIVE ?= " ${@ ('${DEPLOY_DIR_IMAGE}/' + d.getVar('INITRD_IMAGE', expand=True) + '-${MACHINE}.cpio.gz') if d.getVar('INITRD_IMAGE', True) else ''}"
-
-do_uefiapp[depends] += " \
-                         intel-microcode:do_deploy \
-                         systemd-boot:do_deploy \
-                         virtual/kernel:do_deploy \
-                       "
-
-# INITRD_IMAGE is added to INITRD_LIVE, which we use to create our initrd, so depend on it if it is set
-do_uefiapp[depends] += "${@ '${INITRD_IMAGE}:do_image_complete' if d.getVar('INITRD_IMAGE') else ''}"
-
-# The image does without traditional bootloader.
-# In its place, instead, it uses a single UEFI executable binary, which is
-# composed by:
-#   - an UEFI stub
-#     The linux kernel can generate a UEFI stub, however the one from systemd-boot can fetch
-#     the command line from a separate section of the EFI application, avoiding the need to
-#     rebuild the kernel.
-#   - the kernel
-#   - an initramfs (optional)
-
-def create_uefiapp(d, uuid=None, app_suffix=''):
-    import glob, re
-    from subprocess import check_call
-
-    build_dir = d.getVar('B')
-    deploy_dir_image = d.getVar('DEPLOY_DIR_IMAGE')
-    image_link_name = d.getVar('IMAGE_LINK_NAME')
-
-    cmdline = '%s/cmdline.txt' % build_dir
-    linux = '%s/%s' % (deploy_dir_image, d.getVar('KERNEL_IMAGETYPE'))
-    initrd = '%s/initrd' % build_dir
-
-    stub_path = '%s/linux*.efi.stub' % deploy_dir_image
-    stub = glob.glob(stub_path)[0]
-    m = re.match(r"\S*(ia32|x64)(.efi)\S*", os.path.basename(stub))
-    app = "boot%s%s%s" % (m.group(1), app_suffix, m.group(2))
-    executable = '%s/%s.%s' % (deploy_dir_image, image_link_name, app)
-
-    if d.getVar('INITRD_LIVE'):
-        with open(initrd, 'wb') as dst:
-            for cpio in d.getVar('INITRD_LIVE').split():
-                with open(cpio, 'rb') as src:
-                    dst.write(src.read())
-        initrd_cmd = "--add-section .initrd=%s --change-section-vma .initrd=0x3000000 " % initrd
-    else:
-        initrd_cmd = ""
-
-    root = 'root=PARTUUID=%s' % uuid if uuid else ''
-
-    with open(cmdline, 'w') as f:
-        f.write('%s %s' % (d.getVar('APPEND'), root))
-
-    objcopy_cmd = ("objcopy "
-        "--add-section .cmdline=%s --change-section-vma .cmdline=0x30000 "
-        "--add-section .linux=%s --change-section-vma .linux=0x40000 "
-        "%s %s %s") % \
-        (cmdline, linux, initrd_cmd, stub, executable)
-
-    check_call(objcopy_cmd, shell=True)
-
-python create_uefiapps () {
-    # We must clean up anything that matches the expected output pattern, to ensure that
-    # the next steps do not accidentally use old files.
-    import glob
-    pattern = d.expand('${DEPLOY_DIR_IMAGE}/${IMAGE_LINK_NAME}.boot*.efi')
-    for old_efi in glob.glob(pattern):
-        os.unlink(old_efi)
-    uuid = d.getVar('DISK_SIGNATURE_UUID')
-    create_uefiapp(d, uuid=uuid)
-}
-
-# This is intentionally split into different parts. This way, derived
-# classes or images can extend the individual parts. We can also use
-# whatever language (shell script or Python) is more suitable.
-python do_uefiapp() {
-    bb.build.exec_func('create_uefiapps', d)
-}
-
-do_uefiapp[vardeps] += "APPEND DISK_SIGNATURE_UUID INITRD_LIVE KERNEL_IMAGETYPE IMAGE_LINK_NAME"
-
-uefiapp_deploy_at() {
-    dest=$1
-    for i in ${DEPLOY_DIR_IMAGE}/${IMAGE_LINK_NAME}.boot*.efi; do
-        target=`basename $i`
-        target=`echo $target | sed -e 's/${IMAGE_LINK_NAME}.//'`
-        cp  --preserve=timestamps -r $i $dest/$target
-    done
-}
-
-fakeroot do_uefiapp_deploy() {
-    rm -rf ${IMAGE_ROOTFS}/boot/*
-    dest=${IMAGE_ROOTFS}/boot/EFI/BOOT
-    mkdir -p $dest
-    uefiapp_deploy_at $dest
-}
-
-do_uefiapp_deploy[depends] += "${PN}:do_uefiapp virtual/fakeroot-native:do_populate_sysroot"
-
-
-# This decides when/how we add our tasks to the image
-python () {
-    image_fstypes = d.getVar('IMAGE_FSTYPES', True)
-    initramfs_fstypes = d.getVar('INITRAMFS_FSTYPES', True)
-
-    # Don't add any of these tasks to initramfs images
-    if initramfs_fstypes not in image_fstypes:
-        bb.build.addtask('uefiapp', 'do_image', 'do_rootfs', d)
-        bb.build.addtask('uefiapp_deploy', 'do_image', 'do_rootfs', d)
-}
-
-SIGN_AFTER ?= "do_uefiapp"
-SIGN_BEFORE ?= "do_uefiapp_deploy"
-SIGNING_DIR ?= "${DEPLOY_DIR_IMAGE}"
-SIGNING_BINARIES ?= "${IMAGE_LINK_NAME}.boot*.efi"
-inherit uefi-sign
-
-# Legacy hddimg support below this line
-efi_hddimg_populate() {
-    uefiapp_deploy_at "$1"
-}
-
-build_efi_cfg() {
-    # The command line is built into the combo app, so this is a null op
-    :
-}
-
-populate_kernel:append() {
-    # The kernel and initrd are built into the app, so we don't need these
-    if [ -f $dest/initrd ]; then
-        rm $dest/initrd
-    fi
-    if [ -f $dest/vmlinuz ]; then
-        rm $dest/vmlinuz
-    fi
-}
-
-IMAGE_FEATURES[validitems] += "secureboot"

classes/uefi-sign.bbclass

@@ -1,50 +0,0 @@
-# By default, sign all .efi binaries in ${B} after compiling and before deploying
-SIGNING_DIR ?= "${B}"
-SIGNING_BINARIES ?= "*.efi"
-SIGN_AFTER ?= "do_compile"
-SIGN_BEFORE ?= "do_deploy"
-
-python () {
-    import os
-    import hashlib
-
-    # Ensure that if the signing key or cert change, we rerun the uefiapp process
-    if bb.utils.contains('IMAGE_FEATURES', 'secureboot', True, False, d):
-        for varname in ('SECURE_BOOT_SIGNING_CERT', 'SECURE_BOOT_SIGNING_KEY'):
-            filename = d.getVar(varname)
-            if filename is None:
-                bb.fatal('%s is not set.' % varname)
-            if not os.path.isfile(filename):
-                bb.fatal('%s=%s is not a file.' % (varname, filename))
-            with open(filename, 'rb') as f:
-                data = f.read()
-            hash = hashlib.sha256(data).hexdigest()
-            d.setVar('%s_HASH' % varname, hash)
-
-            # Must reparse and thus rehash on file changes.
-            bb.parse.mark_dependency(d, filename)
-
-        bb.build.addtask('uefi_sign', d.getVar('SIGN_BEFORE'), d.getVar('SIGN_AFTER'), d)
-
-        # Original binary needs to be regenerated if the hash changes since we overwrite it
-        # SIGN_AFTER isn't necessarily when it gets generated, but its our best guess
-        d.appendVarFlag(d.getVar('SIGN_AFTER'), 'vardeps', 'SECURE_BOOT_SIGNING_CERT_HASH SECURE_BOOT_SIGNING_KEY_HASH')
-}
-
-do_uefi_sign() {
-    if [ -f ${SECURE_BOOT_SIGNING_KEY} ] && [ -f ${SECURE_BOOT_SIGNING_CERT} ]; then
-        for i in `find ${SIGNING_DIR}/ -name '${SIGNING_BINARIES}'`; do
-            sbsign --key ${SECURE_BOOT_SIGNING_KEY} --cert ${SECURE_BOOT_SIGNING_CERT} $i
-            sbverify --cert ${SECURE_BOOT_SIGNING_CERT} $i.signed
-            mv $i.signed $i
-        done
-    fi
-}
-
-do_uefi_sign[depends] += "sbsigntool-native:do_populate_sysroot"
-
-do_uefi_sign[vardeps] += "SECURE_BOOT_SIGNING_CERT_HASH \
-                          SECURE_BOOT_SIGNING_KEY_HASH  \
-                          SIGNING_BINARIES SIGNING_DIR  \
-                          SIGN_BEFORE SIGN_AFTER        \
-                         "

conf/include/maintainers.inc

@@ -7,11 +7,11 @@ RECIPE_MAINTAINER:pn-core-image-tiny = "Naveen Saini <naveen.kumar.saini@intel.c
 RECIPE_MAINTAINER:pn-core-image-minimal-initramfs = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-embree = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-gmmlib = "Lim Siew Hoon <siew.hoon.lim@intel.com>"
-RECIPE_MAINTAINER:pn-hdcp = "Naveen Saini <naveen.kumar.saini@intel.com>"
-RECIPE_MAINTAINER:pn-intel-graphics-compiler = "Naveen Saini <naveen.kumar.saini@intel.com>"
+RECIPE_MAINTAINER:pn-intel-cmt-cat = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-intel-compute-runtime = "Naveen Saini <naveen.kumar.saini@intel.com>"
+RECIPE_MAINTAINER:pn-intel-crypto-mb = "Anuj Mittal <anuj.mittal@intel.com>"
+RECIPE_MAINTAINER:pn-intel-graphics-compiler = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-intel-media-driver = "Lim Siew Hoon <siew.hoon.lim@intel.com>"
-RECIPE_MAINTAINER:pn-intel-mediasdk = "Lim Siew Hoon <siew.hoon.lim@intel.com>"
 RECIPE_MAINTAINER:pn-intel-microcode = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-intel-vaapi-driver = "Lim Siew Hoon <siew.hoon.lim@intel.com>"
 RECIPE_MAINTAINER:pn-ipmctl = "Anuj Mittal <anuj.mittal@intel.com>"
@@ -21,17 +21,15 @@ RECIPE_MAINTAINER:pn-itt = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-ixgbe = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-ixgbevf = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-iucode-tool = "Anuj Mittal <anuj.mittal@intel.com>"
-RECIPE_MAINTAINER:pn-jhi = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-level-zero = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-libipt = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-libva-intel = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-libva-intel-utils = "Anuj Mittal <anuj.mittal@intel.com>"
-RECIPE_MAINTAINER:pn-libyami = "Anuj Mittal <anuj.mittal@intel.com>"
-RECIPE_MAINTAINER:pn-libyami-utils = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-libxcam = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-linux-intel = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-linux-intel-rt = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-linux-intel-dev = "Naveen Saini <naveen.kumar.saini@intel.com>"
+RECIPE_MAINTAINER:pn-linux-npu-driver = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-lms = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-metee = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-metrics-discovery = "Naveen Saini <naveen.kumar.saini@intel.com>"
@@ -40,17 +38,9 @@ RECIPE_MAINTAINER:pn-onednn = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-onedpl = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-onevpl = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-onevpl-intel-gpu = "Yew Chang Ching <chang.ching.yew@intel.com>"
-RECIPE_MAINTAINER:pn-open-model-zoo = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-opencl-clang = "Naveen Saini <naveen.kumar.saini@intel.com>"
-RECIPE_MAINTAINER:pn-openvino-inference-engine = "Anuj Mittal <anuj.mittal@intel.com>"
-RECIPE_MAINTAINER:pn-openvino-model-optimizer = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-openvkl = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-ospray = "Naveen Saini <naveen.kumar.saini@intel.com>"
-RECIPE_MAINTAINER:pn-ovmf-shell-image-enrollkeys = "Naveen Saini <naveen.kumar.saini@intel.com>"
 RECIPE_MAINTAINER:pn-rkcommon = "Naveen Saini <naveen.kumar.saini@intel.com>"
-RECIPE_MAINTAINER:pn-sbsigntool-native = "Anuj Mittal <anuj.mittal@intel.com>"
-RECIPE_MAINTAINER:pn-secureboot-selftest-image-signed = "Anuj Mittal <anuj.mittal@intel.com>"
-RECIPE_MAINTAINER:pn-secureboot-selftest-image-unsigned = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-thermald = "Anuj Mittal <anuj.mittal@intel.com>"
 RECIPE_MAINTAINER:pn-xf86-video-ast = "Anuj Mittal <anuj.mittal@intel.com>"
-RECIPE_MAINTAINER:pn-zlib-intel = "Naveen Saini <naveen.kumar.saini@intel.com>"

conf/layer.conf

@@ -10,7 +10,8 @@ BBFILE_PATTERN_intel := "^${LAYERDIR}/"
 BBFILE_PRIORITY_intel = "5"
 
 # Additional license directories.
-LICENSE_PATH += "${LAYERDIR}/custom-licenses"
+CUSTOM_LICENSES_PATH = "${LAYERDIR}/custom-licenses"
+LICENSE_PATH += "${CUSTOM_LICENSES_PATH}"
 
 LAYERDEPENDS_intel = "core"
 LAYERRECOMMENDS_intel = "dpdk"
@@ -18,7 +19,7 @@ LAYERRECOMMENDS_intel = "dpdk"
 # This should only be incremented on significant changes that will
 # cause compatibility issues with other layers
 LAYERVERSION_intel = "5"
-LAYERSERIES_COMPAT_intel = "dunfell gatesgarth hardknott honister"
+LAYERSERIES_COMPAT_intel = "scarthgap whinlatter"
 
 BBFILES_DYNAMIC += " \
     clang-layer:${LAYERDIR}/dynamic-layers/clang-layer/*/*/*.bb \
@@ -31,10 +32,6 @@ BBFILES_DYNAMIC += " \
 
 require ${LAYERDIR}/conf/include/maintainers.inc
 
-PREFERRED_PROVIDER_zlib ?= "zlib"
-PREFERRED_PROVIDER_zlib-native ?= "zlib-native"
-PREFERRED_PROVIDER_nativesdk-zlib ?= "nativesdk-zlib"
-
 # Use the libva from OE-Core when layer is included but no MACHINE
 # from meta-intel is being used.
 PREFERRED_PROVIDER_libva ?= "libva"
@@ -45,4 +42,4 @@ PREFERRED_PROVIDER_libva-utils ?= "libva-utils"
 PREFERRED_PROVIDER_libva-utils-native ?= "libva-utils-native"
 PREFERRED_PROVIDER_nativesdk-libva-utils ?= "nativesdk-libva-utils"
 
-X86_TUNE_DIR = "${@bb.utils.contains('LAYERSERIES_CORENAMES', 'honister', 'include/x86', 'include', d)}"
+addpylib ${LAYERDIR}/lib oeqa

conf/machine/include/intel-common-pkgarch.inc

@@ -11,5 +11,5 @@ PACKAGE_ARCH:pn-intel-microcode = "${INTEL_COMMON_PACKAGE_ARCH}"
 PACKAGE_ARCH:pn-backport-iwlwifi = "${INTEL_COMMON_PACKAGE_ARCH}"
 PACKAGE_ARCH:pn-ixgbe = "${INTEL_COMMON_PACKAGE_ARCH}"
 PACKAGE_ARCH:pn-ixgbevf = "${INTEL_COMMON_PACKAGE_ARCH}"
-PACKAGE_EXTRA_ARCHS:append += "${INTEL_COMMON_PACKAGE_ARCH}"
+PACKAGE_EXTRA_ARCHS:append = " ${INTEL_COMMON_PACKAGE_ARCH}"
 MACHINEOVERRIDES =. "${INTEL_COMMON_PACKAGE_ARCH}:"

conf/machine/include/intel-core2-32-common.inc

@@ -3,5 +3,5 @@
 #
 
 DEFAULTTUNE ?= "core2-32"
-require conf/machine/${X86_TUNE_DIR}/tune-core2.inc
-require conf/machine/${X86_TUNE_DIR}/x86-base.inc
+require conf/machine/include/x86/tune-core2.inc
+require conf/machine/include/x86/x86-base.inc

conf/machine/include/intel-corei7-64-common.inc

@@ -3,5 +3,5 @@
 #
 
 DEFAULTTUNE ?= "corei7-64"
-require conf/machine/${X86_TUNE_DIR}/tune-corei7.inc
-require conf/machine/${X86_TUNE_DIR}/x86-base.inc
+require conf/machine/include/x86/tune-corei7.inc
+require conf/machine/include/x86/x86-base.inc

conf/machine/include/meta-intel.inc

@@ -7,15 +7,10 @@
 PREFERRED_PROVIDER_virtual/kernel ?= "linux-intel"
 PREFERRED_PROVIDER_virtual/kernel:poky-tiny ?= "linux-intel"
 
-# Only use the Intel-tuned zlib for target builds to improve reuse
-PREFERRED_PROVIDER_zlib = "zlib-intel"
-PREFERRED_PROVIDER_zlib-native = "zlib-native"
-PREFERRED_PROVIDER_nativesdk-zlib = "nativesdk-zlib"
-
-PREFERRED_VERSION_linux-intel ?= "5.10%"
-PREFERRED_VERSION_linux-intel-rt ?= "5.10%"
-PREFERRED_VERSION_linux-intel:poky-altcfg ?= "5.4%"
-PREFERRED_VERSION_linux-intel-rt:poky-altcfg ?= "5.4%"
+PREFERRED_VERSION_linux-intel ?= "6.12%"
+PREFERRED_VERSION_linux-intel-rt ?= "6.12%"
+PREFERRED_VERSION_linux-intel:poky-altcfg ?= "6.12%"
+PREFERRED_VERSION_linux-intel-rt:poky-altcfg ?= "6.12%"
 
 # Need to point to latest version of libva needed for media components
 PREFERRED_PROVIDER_libva = "libva-intel"
@@ -26,13 +21,6 @@ PREFERRED_PROVIDER_libva-utils = "libva-intel-utils"
 PREFERRED_PROVIDER_libva-utils-native = "libva-intel-utils-native"
 PREFERRED_PROVIDER_nativesdk-libva-utils = "nativesdk-libva-intel-utils"
 
-PREFERRED_VERSION_opencl-clang ?= "${@bb.utils.contains('LLVMVERSION', '10.0.1', '10.0.0', \
-                                            bb.utils.contains('LLVMVERSION', '11.1.0', '11.0.0', \
-                                            bb.utils.contains('LLVMVERSION', '12.0.0', '12.0.0', '13.0.0', d), d), d)}"
-PREFERRED_VERSION_opencl-clang-native ?= "${@bb.utils.contains('LLVMVERSION', '10.0.1', '10.0.0', \
-                                            bb.utils.contains('LLVMVERSION', '11.1.0', '11.0.0', \
-                                            bb.utils.contains('LLVMVERSION', '12.0.0', '12.0.0', '13.0.0', d), d), d)}"
-
 XSERVER_X86_ASPEED_AST = "xf86-video-ast \
            "
 
@@ -41,7 +29,7 @@ MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append = "${@bb.utils.contains('MACHINE_FEATURE
 
 # recommended extra packages common to all intel machines
 MACHINE_EXTRA_RRECOMMENDS:append = " kernel-modules linux-firmware"
-MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS:append = " kernel-module-i915 linux-firmware-i915"
+MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS:append = " kernel-module-i915 linux-firmware-i915 kernel-module-igc kernel-module-r8152"
 
 # for the early boot time kernel microcode loading support,
 # merge the microcode data in the final initrd image.

conf/machine/include/qemu-intel.inc

@@ -2,7 +2,7 @@
 # distro content (in particular the kernel) less than qemu.inc.
 
 # Ensure that qemu gets built when building images.
-EXTRA_IMAGEDEPENDS += "qemu-native qemu-helper-native"
+EXTRA_IMAGEDEPENDS += "qemu-system-native qemu-helper-native:do_addto_recipe_sysroot"
 
 # Build ovmf firmware for uefi support in qemu.
 EXTRA_IMAGEDEPENDS += "ovmf"

conf/machine/include/qemuboot-intel.inc

@@ -13,7 +13,6 @@ QB_CPU:intel-skylake-64 = "-cpu Skylake-Client"
 QB_CPU_KVM:intel-skylake-64 = "-cpu Skylake-Client"
 
 QB_AUDIO_DRV = "alsa"
-QB_AUDIO_OPT = "-soundhw ac97,es1370"
-QB_KERNEL_CMDLINE_APPEND = "vga=0 uvesafb.mode_option=640x480-32 oprofile.timer=1 uvesafb.task_timeout=-1"
-# Add the 'virtio-rng-pci' device otherwise the guest may run out of entropy
-QB_OPT_APPEND = "-vga vmware -usb -usbdevice tablet -device virtio-rng-pci"
+QB_AUDIO_OPT = "-device AC97"
+QB_KERNEL_CMDLINE_APPEND = " oprofile.timer=1"
+QB_OPT_APPEND = " -usb -usbdevice tablet "

conf/machine/include/tune-skylake.inc

@@ -1,48 +0,0 @@
-# Settings for the GCC(1) cpu-type "skylake":
-#
-#     Intel Skylake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
-#     SSE4.2, AVX, AVX2 and POPCNT instruction set support.
-#
-# This tune is recommended for Intel Skylake CPU (and beyond).
-#
-DEFAULTTUNE ?= "skylake-64"
-
-# Include the previous tune to pull in PACKAGE_EXTRA_ARCHS
-require conf/machine/${X86_TUNE_DIR}/tune-corei7.inc
-
-# Extra tune features
-TUNEVALID[skylake] = "Enable skylake specific processor optimizations"
-TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'skylake', ' -march=skylake ${SKYLAKE_TUNE} -mfpmath=sse', '', d)}"
-
-# Extra tune selections
-
-AVAILTUNES += "skylake-64"
-TUNE_FEATURES:tune-skylake-64 = "${TUNE_FEATURES:tune-x86-64} skylake"
-BASE_LIB:tune-skylake-64 = "lib64"
-TUNE_PKGARCH:tune-skylake-64 = "skylake-64"
-PACKAGE_EXTRA_ARCHS:tune-skylake-64 = "${PACKAGE_EXTRA_ARCHS:tune-core2-64} skylake-64"
-QEMU_EXTRAOPTIONS_skylake-64 = " -cpu Skylake-Client"
-
-
-# Disable QEMU usermode by default (get avx2)
-MACHINE_FEATURES:remove = "qemu-usermode"
-
-# If qemu-usermode is enabled, we have to disable avx2 ISA extensions, but we can keep mtune as skylake vs generic
-SKYLAKE_TUNE .= "${@bb.utils.contains('MACHINE_FEATURES', 'qemu-usermode', ' -mtune=skylake ${QEMU_UNAVAILABLE_ISA}', '-mtune=generic -mavx2', d)}"
-
-QEMU_UNAVAILABLE_ISA = " \
--mno-avx \
--mno-avx2 \
--mno-avx512f \
--mno-avx512er \
--mno-avx512cd \
--mno-avx512pf \
--mno-avx512dq \
--mno-avx512bw \
--mno-avx512vl \
--mno-avx512ifma \
--mno-avx512vbmi \
--mno-avx512vbmi2 \
--mno-avx512vnni \
--mno-avx512bitalg \
-"

conf/machine/intel-corei7-64.conf

@@ -11,10 +11,11 @@ MACHINE_FEATURES += "pcbios efi"
 MACHINE_FEATURES += "wifi 3g nfc"
 MACHINE_FEATURES += "intel-ucode"
 
-MACHINE_HWCODECS ?= "${@bb.utils.contains('TUNE_FEATURES', 'mx32', '', 'intel-media-driver intel-mediasdk', d)} gstreamer1.0-vaapi"
+MACHINE_HWCODECS ?= "${@bb.utils.contains('TUNE_FEATURES', 'mx32', '', 'intel-media-driver vpl-gpu-rt', d)} gstreamer1.0-vaapi"
 
 # Enable optional dpdk:
 COMPATIBLE_MACHINE:pn-dpdk = "intel-corei7-64"
+COMPATIBLE_MACHINE:pn-dpdk-module = "intel-corei7-64"
 
 XSERVER ?= "${XSERVER_X86_BASE} \
             ${XSERVER_X86_EXT} \

conf/machine/intel-skylake-64.conf

@@ -4,17 +4,18 @@
 #@DESCRIPTION: Machine configuration for 64 bit Intel Skylake CPU (and later) with MMX, SSE, SSE2, SSE3, SSE4.1, SSE4.2, AVX, and AVX2 instruction set support. Supports a moderately wide range of drivers that should boot and be usable on "typical" hardware.
 
 require conf/machine/include/meta-intel.inc
-require conf/machine/${X86_TUNE_DIR}/x86-base.inc
-require conf/machine/include/tune-skylake.inc
+require conf/machine/include/x86/x86-base.inc
+require conf/machine/include/x86/tune-x86-64-v3.inc
 require conf/machine/include/intel-common-pkgarch.inc
 
 MACHINE_FEATURES += "efi"
 MACHINE_FEATURES += "wifi 3g nfc"
 MACHINE_FEATURES += "intel-ucode"
 
-MACHINE_HWCODECS ?= "intel-media-driver intel-mediasdk gstreamer1.0-vaapi"
+MACHINE_HWCODECS ?= "intel-media-driver vpl-gpu-rt gstreamer1.0-vaapi"
 
 COMPATIBLE_MACHINE:pn-dpdk = "intel-skylake-64"
+COMPATIBLE_MACHINE:pn-dpdk-module = "intel-skylake-64"
 
 XSERVER ?= "${XSERVER_X86_BASE} \
             ${XSERVER_X86_EXT} \

custom-licenses/EULA

@@ -0,0 +1,392 @@
+Intel End User License Agreement for Developer Tools (Version October 2021)
+
+IMPORTANT NOTICE - PLEASE READ AND AGREE BEFORE DOWNLOADING, INSTALLING, COPYING
+OR USING
+
+This Agreement is between you, or the company or other legal entity that you
+represent and warrant you have the legal authority to bind, (each, "You" or
+"Your") and Intel Corporation and its subsidiaries (collectively, "Intel")
+regarding Your use of the Materials. By downloading, installing, copying or
+using the Materials, You agree to be bound by the terms of this Agreement. If
+You do not agree to the terms of this Agreement, or do not have legal authority
+or required age to agree to them, do not download, install, copy or use the
+Materials.
+
+1. LICENSE DEFINITIONS.
+
+ A. "Cloud Provider" means a third party service provider offering a cloud-based
+    platform, infrastructure, application or storage services, such as Microsoft
+    Azure or Amazon Web Services, which You may only utilize to host the 
+    Materials subject to the restrictions set forth in Section 2.3 B.
+
+ B. "Derivative Work" means a derivative work, as defined in 17 U.S.C. 101, of
+    the Source Code.
+
+ C. "Executable Code" means computer programming code in binary form suitable
+    for machine execution by a processor without the intervening steps of
+    interpretation or compilation.
+
+ D. "Materials" mean the software, documentation, the software product serial
+    number, and other collateral, including any updates, made available to You 
+    by Intel under this Agreement. Materials include Redistributables, 
+    Executable Code, Source Code, Sample Source Code, and Pre-Release Materials, 
+    but do not include Third Party Software.
+
+ E. "Pre-Release Materials" mean the Materials, or portions of the Materials,
+    that are identified (in the product release notes, on Intel's download 
+    website for the Materials or elsewhere) or labeled as pre-release, 
+    prototype, alpha or beta code and, as such, are deemed to be pre-release 
+    code (i) which may not be fully functional or tested and may contain bugs or 
+    errors; (ii) which Intel may substantially modify in its development of a 
+    production version; or (iii) for which Intel makes no assurances that it 
+    will ever develop or make a production version generally available. 
+    Pre-Release Materials are subject to the terms of Section 3.2.
+
+ F. "Reciprocal Open Source Software" means any software that is subject to a
+    license which requires that (i) it must be distributed in source code form;
+    (ii) it must be licensed under the same open source license terms; and (iii)
+    its derivative works must be licensed under the same open source license 
+    terms. Examples of this type of license are the GNU General Public License 
+    or the Mozilla Public License.
+
+ G. "Redistributables" mean the files (if any) listed in the "redist.txt,"
+    "redist-rt.txt" or similarly-named text files that may be included in the
+    Materials. Redistributables include Sample Source Code.
+
+ H. "Sample Source Code" means those portions of the Materials that are Source
+    Code and are identified as sample code. Sample Source Code may not have been
+    tested or validated by Intel and is provided purely as a programming example.
+
+ I. "Source Code" means the software portion of the Materials provided in human
+    readable format.
+
+ J. "Third Party Software" mean the files (if any) listed in the
+    "third-party-software.txt" or other similarly-named text file that may be
+    included in the Materials for the applicable software. Third Party Software 
+    is subject to the terms of Section 2.2.
+
+ K. "Your Product" means one or more applications, products or projects
+    developed by or for You using the Materials.
+
+2. LICENSE GRANTS.
+
+2.1 License to the Materials. Subject to the terms and conditions of this
+    Agreement, Intel grants You a non-exclusive, worldwide, non-assignable,
+    non-sublicensable, limited right and license under its copyrights, to:
+
+ A. reproduce internally a reasonable number of copies of the Materials for Your
+    personal or business use;
+
+ B. use the Materials solely for Your personal or business use to develop Your
+    Product, in accordance with the documentation included as part of the
+    Materials;
+
+ C. modify or create Derivative Works only of the Redistributables, or any
+    portions, that are provided to You in Source Code;
+
+ D. distribute (directly and through Your distributors, resellers, and other
+    channel partners, if applicable), the Redistributables, including any
+    modifications to or Derivative Works of the Redistributables or any portions
+    made pursuant to Section 2.1.C subject to the following conditions:
+
+  (1) Any distribution of the Redistributables must only be as part of Your
+      Product which must add significant primary functionality different than 
+      that of the Redistributables themselves;
+
+  (2) You must only distribute the Redistributables originally provided to You
+      by Intel only in Executable Code subject to a license agreement that 
+      prohibits reverse engineering, decompiling or disassembling the 
+      Redistributables;
+
+  (3) This distribution right includes a limited right to sublicense only the
+      Intel copyrights in the Redistributables and only to the extent necessary 
+      to perform, display, and distribute the Redistributables (including Your
+      modifications and Derivative Works of the Redistributables provided in 
+      Source Code) solely as incorporated in Your Product; and
+
+  (4) You: (i) will be solely responsible to Your customers for any update,
+      support obligation or other obligation or liability which may arise from 
+      the distribution of Your Product, (ii) will not make any statement that 
+      Your Product is "certified" or that its performance is guaranteed by Intel 
+      or its suppliers, (iii) will not use Intel's or its suppliers' names or 
+      trademarks to market Your Product, (iv) will comply with any additional 
+      restrictions which are included in the text files with the 
+      Redistributables and in Section 3 below, (v) will indemnify, hold 
+      harmless, and defend Intel and its suppliers from and against any claims 
+      or lawsuits, costs, damages, and expenses, including attorney's fees, that 
+      arise or result from (a) Your modifications or Derivative Works of the 
+      Materials or (b) Your distribution of Your Product.
+
+2.2 Third Party Software. Third Party Software, even if included with the
+    distribution of the Materials, may be governed by separate license terms,
+    including without limitation, third party license terms, open source 
+    software notices and terms, and/or other Intel software license terms. These 
+    separate license terms solely govern Your use of the Third Party Software.
+
+2.3 Third Party Use.
+
+ A. If You are an entity, Your contractors may use the Materials under the
+    license specified in Section 2, provided: (i) their use of the Materials is
+    solely on behalf of and in support of Your business, (ii) they agree to the
+    terms and conditions of this Agreement, and (iii) You are solely responsible
+    for their use, misuse or disclosure of the Materials.
+
+ B. You may utilize a Cloud Provider to host the Materials for You, provided:
+    (i) the Cloud Provider may only host the Materials for Your exclusive use 
+   and may not use the Materials for any other purpose whatsoever, including the
+   restriction set forth in Section 3.1(xi); (ii) the Cloud Provider's use of 
+   the Materials must be solely on behalf of and in support of Your Product, and 
+   (iii) You will indemnify, hold harmless, and defend Intel and its suppliers 
+   from and against any claims or lawsuits, costs, damages, and expenses, 
+   including attorney's fees, that arise or result from Your Cloud Provider's 
+   use, misuse or disclosure of the Materials.
+
+3. LICENSE CONDITIONS.
+
+3.1 Restrictions. Except as expressly provided in this Agreement, You may NOT:
+    (i) use, reproduce, disclose, distribute, or publicly display the 
+    Materials; (ii) share, publish, rent or lease the Materials to any third 
+    party; (iii) assign this Agreement or transfer the Materials; (iv) modify, 
+    adapt, or translate the Materials in whole or in part; (v) reverse engineer, 
+    decompile, or disassemble the Materials, or otherwise attempt to derive the 
+    source code for the software; (vi) work around any technical limitations in 
+    the Materials; (vii) distribute, sublicense or transfer any Source Code, 
+    modifications or Derivative Works of any Source Code to any third party; 
+    (viii) remove, minimize, block or modify any notices of Intel or its 
+    suppliers in the Materials; (ix) include the Redistributables in malicious, 
+    deceptive, or unlawful programs or products or use the Materials in any way 
+    that is against the law; (x) modify, create a Derivative Work, link, or 
+    distribute the Materials so that any part of it becomes Reciprocal Open 
+    Source Software; (xi) use the Materials directly or indirectly for SaaS 
+    services or service bureau purposes (i.e., a service that allows use of or 
+    access to the Materials by a third party as part of that service, such as 
+    the salesforce.com service business model).
+
+3.2 Pre-Release Materials. If You receive Pre-Release Materials, You may
+    reproduce a reasonable number of copies and use the Pre-Release Materials 
+    for evaluation and testing purposes only. You may not (i) modify or 
+    incorporate the Pre-Release Materials into Your Product; (ii) continue to 
+    use the Pre-Release Materials once a commercial version is released; or 
+    (iii) disclose to any third party any benchmarks, performance results, or 
+    other information relating to the Pre-Release Materials. Intel may waive 
+    these restrictions in writing at its sole discretion; however, if You decide 
+    to use the Pre-Release Materials in Your Product (even with Intel's waiver), 
+    You acknowledge and agree that You are fully responsible for any and all 
+    issues that result from such use.
+
+3.3 Safety-Critical, and Life-Saving Applications; Indemnity. The Materials may
+    provide information relevant to safety-critical applications 
+    ("Safety-Critical Applications") to allow compliance with functional safety 
+    standards or requirements. You acknowledge and agree that safety is Your 
+    responsibility. To the extent You use the Materials to create, or as part 
+    of, products used in Safety-Critical Applications, it is Your responsibility 
+    to design, manage, and ensure that there are system-level safeguards to 
+    anticipate, monitor, and control system failures, and You agree that You are 
+    solely responsible for all applicable regulatory standards and 
+    safety-related requirements concerning Your use of the Materials in Safety 
+    Critical Applications. 
+
+    Should You use the Materials for Safety-Critical Applications or in any type 
+    of a system or application in which the failure of the Materials could 
+    create a situation where personal injury or death may occur (e.g., medical 
+    systems, life-sustaining or life-saving systems) ("Life-Saving 
+    Applications"), You agree to indemnify, defend, and hold Intel and its 
+    representatives harmless against any claims or lawsuits, costs, damages, and 
+    expenses, including reasonable attorney fees, arising in any way out of Your 
+    use of the Materials in Safety-Critical Applications or Life-Saving 
+    Applications and claims of product liability, personal injury or death 
+    associated with those applications; even if such claims allege that Intel 
+    was negligent or strictly liable regarding the design or manufacture of the 
+    Materials or its failure to warn regarding the Materials.
+
+3.4 Media Format Codecs and Digital Rights Management. You acknowledge and agree
+    that Your use of the Materials or distribution of the Redistributables with 
+    Your Product as permitted by this Agreement may require You to procure 
+    license(s) from third parties that may hold intellectual property rights 
+    applicable to any media decoding, encoding or transcoding technology (e.g., 
+    the use of an audio or video codec) and/or digital rights management 
+    capabilities of the Materials, if any. Should any such additional licenses 
+    be required, You are solely responsible for obtaining any such licenses and 
+    agree to obtain any such licenses at Your own expense.
+
+4. DATA COLLECTION AND PRIVACY.
+
+4.1 Data Collection. The Materials may generate and collect anonymous data
+    and/or provisioning data about the Materials and/or the development 
+    environment and transmit the data to Intel as a one-time event during 
+    installation. Optional data may also be collected by the Materials, however, 
+    You will be provided notice of the request to collect optional data and no 
+    optional data will be collected without Your consent. All data collection by 
+    Intel is performed pursuant to relevant privacy laws, including notice and 
+    consent requirements.
+
+4.2 Intel's Privacy Notice. Intel is committed to respecting Your privacy. To
+    learn more about Intel's privacy practices, please visit
+    http://www.intel.com/privacy.
+
+5. OWNERSHIP. Title to the Materials and all copies remain with Intel or its
+   suppliers. The Materials are protected by intellectual property rights,
+   including without limitation, United States copyright laws and international
+   treaty provisions. You will not remove any copyright or other proprietary
+   notices from the Materials. Except as expressly provided herein, no license 
+   or right is granted to You directly or by implication, inducement, estoppel 
+   or otherwise; specifically, Intel does not grant any express or implied right 
+   to You under Intel patents, copyrights, trademarks, or trade secrets.
+
+6. NO WARRANTY AND NO SUPPORT.
+
+6.1 No Warranty. Disclaimer. Intel disclaims all warranties of any kind and the
+    terms and remedies provided in this Agreement are instead of any other 
+    warranty or condition, express, implied or statutory, including those 
+    regarding merchantability, fitness for any particular purpose, 
+    non-infringement or any warranty arising out of any course of dealing, usage 
+    of trade, proposal, specification or sample. Intel does not assume (and does 
+    not authorize any person to assume on its behalf) any liability.
+
+6.2 No Support; Priority Support. Intel may make changes to the Materials, or to
+    items referenced therein, at any time without notice, but is not obligated 
+    to support, update or provide training for the Materials under the terms of 
+    this Agreement. Intel offers free community and paid priority support 
+    options. More information on these support options can be found at:
+    https://software.intel.com/content/www/us/en/develop/support/priority-support.html.
+
+7. LIMITATION OF LIABILITY.
+
+7.1 Intel will not be liable for any of the following losses or damages (whether
+    such losses or damages were foreseen, foreseeable, known or otherwise):  (i)
+    loss of revenue; (ii) loss of actual or anticipated profits; (iii) loss of 
+    the use of money; (iv) loss of anticipated savings; (v) loss of business; 
+    (vi) loss of opportunity; (vii) loss of goodwill; (viii) loss of use of the 
+    Materials; (ix) loss of reputation; (x) loss of, damage to, or corruption of 
+    data; or (xi) any indirect, incidental, special or consequential loss of 
+    damage however caused (including loss or damage of the type specified in 
+    this Section 7).
+
+7.2 Intel's total cumulative liability to You, including for direct damages for
+    claims relating to this Agreement, and whether for breach of contract,
+    negligence, or for any other reason, will not exceed $100.
+
+7.3 You acknowledge that the limitations of liability provided in this Section 7
+    are an essential part of this Agreement. You agree that the limitations of
+    liability provided in this Agreement with respect to Intel will be conveyed 
+    to and made binding upon any customer of Yours that acquires the 
+    Redistributables.
+
+8. USER SUBMISSIONS. Should you provide Intel with comments, modifications,
+   corrections, enhancements or other input ("Feedback") related to the 
+   Materials, Intel will be free to use, disclose, reproduce, license or 
+   otherwise distribute or exploit the Feedback in its sole discretion without 
+   any obligations or restrictions of any kind, including without limitation, 
+   intellectual property rights or licensing obligations. If You wish to provide 
+   Intel with information that You intend to be treated as confidential 
+   information, Intel requires that such confidential information be provided 
+   pursuant to a non-disclosure agreement ("NDA"); please contact Your Intel 
+   representative to ensure the proper NDA is in place.
+
+9. NON-DISCLOSURE. Information provided by Intel to You may include information
+   marked as confidential. You must treat such information as confidential under
+   the terms of the applicable NDA between Intel and You. If You have not 
+   entered into an NDA with Intel, You must not disclose, distribute or make use 
+   of any information marked as confidential, except as expressly authorized in 
+   writing by Intel. Intel retains all rights in and to its confidential 
+   information specifications, designs, engineering details, discoveries, 
+   inventions, patents, copyrights, trademarks, trade secrets, and other 
+   proprietary rights relating to the Materials. Any breach by You of the 
+   confidentiality obligations provided for in this Section 9 will cause 
+   irreparable injury to Intel for which money damages may be inadequate to 
+   compensate Intel for losses arising from such a breach. Intel may obtain 
+   equitable relief, including injunctive relief, if You breach or threaten to 
+   breach Your confidentiality obligations.
+
+10. TERM AND TERMINATION. This Agreement becomes effective on the date You
+    accept this Agreement and will continue until terminated as provided for in 
+   this Agreement. The term for any Pre-Release Materials terminates upon 
+   release of a commercial version. This Agreement will terminate if You are in 
+   breach of any of its terms and conditions. Upon termination, You will 
+   promptly destroy the Materials and all copies. In the event of termination of 
+   this Agreement, Your license to any Redistributables distributed by You in 
+   accordance with the terms and conditions of this Agreement, prior to the 
+   effective date of such termination, will survive any such termination of this 
+   Agreement. Sections 1, 2.1.D(4)(v), 2.2, 2.3.A(iii), 2.3.B(iii), 3.3, 5, 6, 
+   7, 8, 9, 10 (with respect to these survival provisions in the last sentence), 
+   and 12 will survive expiration or termination of this Agreement.
+
+11. U.S. GOVERNMENT RESTRICTED RIGHTS. The technical data and computer software
+    covered by this license is a "Commercial Item," as such term is defined by 
+    the FAR 2.101 (48 C.F.R. 2.101) and is "commercial computer software" and
+    "commercial computer software documentation" as specified under FAR 12.212 
+    (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicable. 
+    This commercial computer software and related documentation is provided to 
+    end users for use by and on behalf of the U.S. Government with only those 
+    rights as are granted to all other end users pursuant to the terms and 
+    conditions of this Agreement.
+
+12. GENERAL PROVISIONS.
+
+12.1 ENTIRE AGREEMENT. This Agreement contains the complete and exclusive
+     agreement and understanding between the parties concerning the subject 
+     matter of this Agreement, and supersedes all prior and contemporaneous 
+     proposals, agreements, understanding, negotiations, representations, 
+     warranties, conditions, and communications, oral or written, between the 
+     parties relating to the same subject matter. Each party acknowledges and 
+     agrees that in entering into this Agreement it has not relied on, and will 
+     not be entitled to rely on, any oral or written representations, 
+     warranties, conditions, understanding, or communications between the 
+     parties that are not expressly set forth in this Agreement. The express 
+     provisions of this Agreement control over any course of performance, course 
+     of dealing, or usage of the trade inconsistent with any of the provisions 
+     of this Agreement. The provisions of this Agreement will prevail 
+     notwithstanding any different, conflicting, or additional provisions that 
+     may appear on any purchase order, acknowledgement, invoice, or other 
+     writing issued by either party in connection with this Agreement. No 
+     modification or amendment to this Agreement will be effective unless in 
+     writing and signed by authorized representatives of each party, and must 
+     specifically identify this Agreement by its title and version (e.g., "Intel 
+     End User License Agreement for Developer Tools (Version October 2021)"); 
+     except that Intel may make changes to this Agreement as it distributes new 
+     versions of the Materials. When changes are made, Intel will make a new 
+     version of the Agreement available on its website. If You received a copy 
+     of this Agreement translated into another language, the English language 
+     version of this Agreement will prevail in the event of any conflict between 
+     versions.
+
+12.2 EXPORT. You acknowledge that the Materials and all related technical
+     information are subject to export controls and you agree to comply with all 
+     laws and regulations of the United States and other applicable governments 
+     governing export, re-export, import, transfer, distribution, and use of the 
+     Materials. In particular, but without limitation, the Materials may not be 
+     exported or re-exported (i) into any U.S. embargoed countries or (ii) to 
+     any person or entity listed on a denial order published by the U.S. 
+     government or any other applicable governments. By using the Materials, You 
+     represent and warrant that You are not located in any such country or on 
+     any such list. You also agree that You will not use the Materials for, or 
+     sell or transfer them to a third party who is known or suspected to be 
+     involved in, any purposes prohibited by the U.S. government or other 
+     applicable governments, including, without limitation, the development, 
+     design, manufacture, or production of nuclear, missile, chemical or 
+     biological weapons.
+
+12.3 GOVERNING LAW, JURISDICTION, AND VENUE. All disputes arising out of or
+     related to this Agreement, whether based on contract, tort, or any other 
+     legal or equitable theory, will in all respects be governed by, and 
+     construed and interpreted under, the laws of the United States of America 
+     and the State of Delaware, without reference to conflict of laws 
+     principles. The parties agree that the United Nations Convention on 
+     Contracts for the International Sale of Goods (1980) is specifically 
+     excluded from and will not apply to this Agreement. All disputes arising 
+     out of or related to this Agreement, whether based on contract, tort, or 
+     any other legal or equitable theory, will be subject to the exclusive 
+     jurisdiction of the courts of the State of Delaware or of the Federal 
+     courts sitting in that State. Each party submits to the personal 
+     jurisdiction of those courts and waives all objections to that jurisdiction 
+     and venue for those disputes.
+
+12.4 SEVERABILITY. The parties intend that if a court holds that any provision
+     or part of this Agreement is invalid or unenforceable under applicable law, 
+     the court will modify the provision to the minimum extent necessary to make 
+     it valid and enforceable, or if it cannot be made valid and enforceable, 
+     the parties intend that the court will sever and delete the provision or 
+     part from this Agreement. Any change to or deletion of a provision or part 
+     of this Agreement under this Section will not affect the validity or 
+     enforceability of the remainder of this Agreement, which will continue in 
+     full force and effect.

custom-licenses/ISSL

@@ -1,63 +1,73 @@
-Intel Simplified Software License (Version February 2020)
+Intel Simplified Software License (Version August 2021)
 
-Use and Redistribution. You may use and redistribute the software (the “Software”), without modification,
-provided the following conditions are met:
+Use and Redistribution. You may use and redistribute the software (the
+"Software"), without modification, provided the following conditions are met:
 
-* Redistributions must reproduce the above copyright notice and the following terms of use in the Software
-and in the documentation and/or other materials provided with the distribution.
+* Redistributions must reproduce the above copyright notice and the following
+  terms of use in the Software and in the documentation and/or other materials
+  provided with the distribution.
+* Neither the name of Intel nor the names of its suppliers may be used to 
+  endorse or promote products derived from this Software without specific  
+  prior written permission.
+* No reverse engineering, decompilation, or disassembly of this Software is
+  permitted.
 
-* Neither the name of Intel nor the names of its suppliers may be used to endorse or promote products derived
-from this Software without specific prior written permission.
+No other licenses. Except as provided in the preceding section, Intel grants no
+licenses or other rights by implication, estoppel or otherwise to, patent,
+copyright, trademark, trade name, service mark or other intellectual property
+licenses or rights of Intel.
 
-* No reverse engineering, decompilation, or disassembly of this Software is permitted.
+Third party software. The Software may contain Third Party Software. "Third
+Party Software" is open source software, third party software, or other Intel
+software that may be identified in the Software itself or in the files (if any)
+listed in the "third-party-software.txt" or similarly named text file included
+with the Software. Third Party Software, even if included with the distribution
+of the Software, may be governed by separate license terms, including without
+limitation, open source software license terms, third party software license
+terms, and other Intel software license terms. Those separate license terms
+solely govern your use of the Third Party Software, and nothing in this license
+limits any rights under, or grants rights that supersede, the terms of the
+applicable license terms.
 
-Limited patent license. Intel grants you a world-wide, royalty-free, non-exclusive license under patents
-it now or hereafter owns or controls to make, have made, use, import, offer to sell and sell (“Utilize”)
-this Software, but solely to the extent that any such patent is necessary to Utilize the Software alone.
-The patent license shall not apply to any combinations which include this software. No hardware per se
-is licensed hereunder.
+DISCLAIMER. THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT ARE
+DISCLAIMED. THIS SOFTWARE IS NOT INTENDED FOR USE IN SYSTEMS OR APPLICATIONS
+WHERE FAILURE OF THE SOFTWARE MAY CAUSE PERSONAL INJURY OR DEATH AND YOU AGREE
+THAT YOU ARE FULLY RESPONSIBLE FOR ANY CLAIMS, COSTS, DAMAGES, EXPENSES, AND
+ATTORNEYS' FEES ARISING OUT OF ANY SUCH USE, EVEN IF ANY CLAIM ALLEGES THAT
+INTEL WAS NEGLIGENT REGARDING THE DESIGN OR MANUFACTURE OF THE SOFTWARE.
 
-Third party programs. The Software may contain Third Party Programs. “Third Party Programs” are third party
-software, open source software or other Intel software listed in the “third-party-programs.txt” or other similarly
-named text file that is included with the Software. Third Party Programs, even if included with the distribution
-of the Software, may be governed by separate license terms, including without limitation, third party license terms,
-open source software notices and terms, and/or other Intel software license terms. These separate license terms may
-govern your use of the Third Party Programs.
+LIMITATION OF LIABILITY. IN NO EVENT WILL INTEL BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-DISCLAIMER. THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
-BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-AND NON-INFRINGEMENT ARE DISCLAIMED. THIS SOFTWARE IS NOT INTENDED FOR USE IN SYSTEMS OR APPLICATIONS
-WHERE FAILURE OF THE SOFTWARE MAY CAUSE PERSONAL INJURY OR DEATH AND YOU AGREE THAT YOU ARE FULLY RESPONSIBLE
-FOR ANY CLAIMS, COSTS, DAMAGES, EXPENSES, AND ATTORNEYS’ FEES ARISING OUT OF ANY SUCH USE, EVEN IF ANY CLAIM
-ALLEGES THAT INTEL WAS NEGLIGENT REGARDING THE DESIGN OR MANUFACTURE OF THE MATERIALS.
+No support. Intel may make changes to the Software, at any time without notice,
+and is not obligated to support, update or provide training for the Software.
 
-LIMITATION OF LIABILITY. IN NO EVENT WILL INTEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. YOU AGREE TO
-INDEMNIFY AND HOLD INTEL HARMLESS AGAINST ANY CLAIMS AND EXPENSES RESULTING FROM YOUR USE OR UNAUTHORIZED
-USE OF THE SOFTWARE.
+Termination. Your right to use the Software is terminated in the event of your
+breach of this license.
 
-No support. Intel may make changes to the Software, at any time without notice, and is not obligated to
-support, update or provide training for the Software.
+Feedback. Should you provide Intel with comments, modifications, corrections,
+enhancements or other input ("Feedback") related to the Software, Intel will be
+free to use, disclose, reproduce, license or otherwise distribute or exploit the
+Feedback in its sole discretion without any obligations or restrictions of any
+kind, including without limitation, intellectual property rights or licensing
+obligations.
 
-Termination. Intel may terminate your right to use the Software in the event of your breach of this Agreement
-and you fail to cure the breach within a reasonable period of time.
+Compliance with laws. You agree to comply with all relevant laws and regulations
+governing your use, transfer, import or export (or prohibition thereof) of the
+Software.
 
-Feedback. Should you provide Intel with comments, modifications, corrections, enhancements or other input
-(“Feedback”) related to the Software Intel will be free to use, disclose, reproduce, license or otherwise
-distribute or exploit the Feedback in its sole discretion without any obligations or restrictions of any
-kind, including without limitation, intellectual property rights or licensing obligations.
-
-Compliance with laws. You agree to comply with all relevant laws and regulations governing your use,
-transfer, import or export (or prohibition thereof) of the Software.
-
-Governing law. All disputes will be governed by the laws of the United States of America and the State
-of Delaware without reference to conflict of law principles and subject to the exclusive jurisdiction of
-the state or federal courts sitting in the State of Delaware, and each party agrees that it submits to
-the personal jurisdiction and venue of those courts and waives any objections. The United Nations
-Convention on Contracts for the International Sale of Goods (1980) is specifically excluded and will
-not apply to the Software.
-
-*Other names and brands may be claimed as the property of others.
+Governing law. All disputes will be governed by the laws of the United States of
+America and the State of Delaware without reference to conflict of law
+principles and subject to the exclusive jurisdiction of the state or federal
+courts sitting in the State of Delaware, and each party agrees that it submits
+to the personal jurisdiction and venue of those courts and waives any
+objections. The United Nations Convention on Contracts for the International
+Sale of Goods (1980) is specifically excluded and will not apply to the
+Software.

documentation/building_and_booting.md

@@ -0,0 +1,134 @@
+### Building the Intel BSP layers
+
+The intel-common BSP provide a few carefully selected tune options and
+generic hardware support to cover the majority of current Intel CPUs and
+devices. The naming follows the convention of intel-<TUNE>-<BITS>, where
+TUNE is the gcc cpu-type (used with mtune and march typically) and BITS
+is either 32 bit or 64 bit.
+
+In order to build an image with BSP support for a given release, you
+need to clone the meta-intel layer from git repository:
+```
+git clone https://git.yoctoproject.org/meta-intel
+```
+
+Check out the appropriate branch or release tags. The branch name and tags
+would align with Yocto Project
+[Release Codenames](https://wiki.yoctoproject.org/wiki/Releases).
+Assuming meta-intel repository is cloned at the top-level of
+OE-Core build tree, you can build a BSP image by adding the location of
+the meta-intel layer to bblayers.conf:
+```
+BBLAYERS = " \
+  /openembedded-core/meta \
+  /openembedded-core/meta-intel "
+```
+
+To enable a particular machine, add a MACHINE line naming the BSP
+to the local.conf file:
+```
+MACHINE ?= "intel-corei7-64"
+```
+
+where this can be replaced by other MACHINE types available:
+
+ - intel-core2-32
+
+   This BSP is optimized for the Core2 family of CPUs as well as all
+   Atom CPUs prior to the Silvermont core.
+
+ - intel-corei7-64
+
+   This BSP is optimized for Nehalem and later Core and Xeon CPUs as
+   well as Silvermont and later Atom CPUs, such as the Baytrail SoCs.
+
+ - intel-skylake-64
+
+   This BSP uses [x86-64-v3 tuning](https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html).
+
+You should then be able to build an image as such:
+```
+$ source oe-init-build-env
+$ bitbake core-image-sato
+```
+
+At the end of a successful build, you should have an image that
+you can boot from a USB flash drive.
+
+
+## Booting the intel-common BSP images
+
+If you've built your own image, you'll find the bootable
+image in the build/tmp/deploy/images/{MACHINE} directory, where
+'MACHINE' refers to the machine name used in the build.
+
+Under Linux, insert a USB flash drive.  Assuming the USB flash drive
+takes device /dev/sdf, use dd to copy the image to it.  Before the image
+can be burned onto a USB drive, it should be un-mounted. Some Linux distros
+may automatically mount a USB drive when it is plugged in. Using USB device
+/dev/sdf as an example, find all mounted partitions:
+```
+$ mount | grep sdf
+```
+
+and un-mount those that are mounted, for example:
+```
+$ umount /dev/sdf1
+$ umount /dev/sdf2
+```
+
+Now burn the image onto the USB drive:
+```
+$ sudo dd if=core-image-sato-intel-corei7-64.wic of=/dev/sdf status=progress
+$ sync
+$ eject /dev/sdf
+```
+
+This should give you a bootable USB flash device. Insert the device
+into a bootable USB socket on the target, and power on.  This should
+result in a system booted to the Sato graphical desktop.
+
+If you want a terminal, use the arrows at the top of the UI to move to
+different pages of available applications, one of which is named
+'Terminal'.  Clicking that should give you a root terminal.
+
+If you want to ssh into the system, you can use the root terminal to
+ifconfig the IP address and use that to ssh in.  The root password is
+empty, so to log in type 'root' for the user name and hit 'Enter' at
+the Password prompt: and you should be in.
+
+If you find you're getting corrupt images on the USB (it doesn't show
+the syslinux boot: prompt, or the boot: prompt contains strange
+characters), try doing this first:
+```
+$ dd if=/dev/zero of=/dev/sdf bs=1M count=512
+```
+
+## Building the installer image
+
+If you plan to install your image to your target machine, you can build a wic
+based installer image instead of default wic image. To build it, you need to
+add below configuration to local.conf :
+
+```
+WKS_FILE = "image-installer.wks.in"
+IMAGE_FSTYPES:append = " ext4"
+IMAGE_TYPEDEP:wic = "ext4"
+INITRD_IMAGE_LIVE="core-image-minimal-initramfs"
+do_image_wic[depends] += "${INITRD_IMAGE_LIVE}:do_image_complete"
+do_rootfs[depends] += "virtual/kernel:do_deploy"
+IMAGE_BOOT_FILES:append = "\
+    ${KERNEL_IMAGETYPE} \
+     microcode.cpio \
+    ${IMGDEPLOYDIR}/${IMAGE_BASENAME}-${MACHINE}.rootfs.ext4;rootfs.img \
+    ${@bb.utils.contains('EFI_PROVIDER', 'grub-efi', 'grub-efi-bootx64.efi;EFI/BOOT/bootx64.efi', '', d)} \
+    ${@bb.utils.contains('EFI_PROVIDER', 'grub-efi', '${IMAGE_ROOTFS}/boot/EFI/BOOT/grub.cfg;EFI/BOOT/grub.cfg', '', d)} \
+    ${@bb.utils.contains('EFI_PROVIDER', 'systemd-boot', 'systemd-bootx64.efi;EFI/BOOT/bootx64.efi', '', d)} \
+    ${@bb.utils.contains('EFI_PROVIDER', 'systemd-boot', '${IMAGE_ROOTFS}/boot/loader/loader.conf;loader/loader.conf ', '', d)} \
+    ${@bb.utils.contains('EFI_PROVIDER', 'systemd-boot', '${IMAGE_ROOTFS}/boot/loader/entries/boot.conf;loader/entries/boot.conf', '', d)} "
+```
+
+Burn the wic image onto USB flash device, insert the device to target machine
+and power on. This should start the installation process.
+
+

documentation/dpcpp-compiler.md

@@ -0,0 +1,107 @@
+Intel(R) oneAPI DPC++/C++ Compiler (ICX) toolchain
+==========================================================================
+
+Get Started with the Intel oneAPI DPC++/C++ Compiler:
+
+https://www.intel.com/content/www/us/en/developer/tools/oneapi/dpc-compiler.html#
+
+
+Getting Started
+===============
+
+Clone the required layers and include them in bblayers.conf:
+
+```
+git clone https://git.openembedded.org/openembedded-core
+git clone https://git.openembedded.org/bitbake
+git clone https://git.openembedded.org/meta-openembedded
+git clone https://github.com/kraj/meta-clang.git
+git clone https://git.yoctoproject.org/meta-intel
+
+$ source openembedded-core/oe-init-build-env
+
+$ bitbake-layers add-layer ../meta-openembedded/meta-oe/
+$ bitbake-layers add-layer ../meta-intel
+$ bitbake-layers add-layer ../meta-clang
+```
+
+Distro
+======
+
+Note that oneAPI DPC++/C++ compiler currently only works when the vendor string is "oe".
+
+```
+DISTRO ?= "nodistro"
+```
+
+MACHINE configuration
+=====================
+
+```
+MACHINE ?= "intel-skylake-64"
+```
+
+Package installation
+====================
+
+```
+# To include OpenCL driver that might be needed when compiling SYCL programs, include:
+IMAGE_INSTALL:append = " intel-compute-runtime intel-graphics-compiler"
+
+# To install only runtime libraries, include:
+IMAGE_INSTALL:append = " intel-oneapi-dpcpp-cpp-runtime intel-oneapi-dpcpp-cpp-runtime-dev"
+
+# To install the toolchain, include:
+IMAGE_INSTALL:append = " intel-oneapi-dpcpp-cpp intel-oneapi-dpcpp-cpp-dev"
+```
+in local.conf.
+
+Build an image
+==============
+
+```
+$ bitbake core-image-minimal
+```
+
+Including oneAPI C++/DPC++ compiler in generated SDK toolchain
+==============================================================
+
+The compiler is not included in the generated SDK by default. If it is expected to be part of SDK, add ICXSDK = "1" in local.conf:
+
+```
+ICXSDK = "1"
+```
+
+Generate SDK:
+```
+bitbake core-image-minimal -c populate_sdk
+```
+
+
+To setup PATH variables on target
+=================================
+
+Once image is booted successfully, some variables would need to be exported to make sure compiler can be used:
+
+```
+$ source /opt/intel/oneapi/compiler/2022.1.0/env/vars.sh
+
+$ mkdir -p /lib64
+
+$ ln -sf /lib/ld-linux-x86-64.so.2 /lib64/ld-linux-x86-64.so.2
+```
+
+Build application and run
+=========================
+
+To compile a sycl application, for example:
+
+```
+$ icpx --target=x86_64-oe-linux -fsycl simple-sycl-app.c -o simple-sycl-app
+```
+
+To run:
+
+```
+$ ./simple-sycl-app
+```

documentation/openvino.md

@@ -0,0 +1,92 @@
+Build a Yocto Image with OpenVINO™ toolkit
+==========================================
+
+Follow the [Yocto Project official documentation](https://docs.yoctoproject.org/brief-yoctoprojectqs/index.html#compatible-linux-distribution) to set up and configure your host machine to be compatible with BitBake.
+
+## Step 1: Set Up Environment
+
+1. Clone the repositories.
+
+```
+      git clone https://git.yoctoproject.org/git/poky
+      git clone https://github.com/openembedded/meta-openembedded
+      git clone https://git.yoctoproject.org/git/meta-intel
+      git clone https://github.com/intel/meta-openvino
+```
+
+
+2. Set up the OpenEmbedded build environment.
+
+```
+      source poky/oe-init-build-env
+
+```
+
+
+
+3. Add BitBake layers.
+
+
+```
+      bitbake-layers add-layer ../meta-openembedded/meta-oe
+      bitbake-layers add-layer ../meta-openembedded/meta-python
+      bitbake-layers add-layer ../meta-intel
+      bitbake-layers add-layer ../meta-openvino
+
+```
+
+
+4. Set up BitBake configurations.
+   Include extra configuration in the `conf/local.conf` file in your build directory as required.
+
+
+```
+      MACHINE = "intel-skylake-64"
+
+      # Enable building OpenVINO Python API.
+      # This requires meta-python layer to be included in bblayers.conf.
+      PACKAGECONFIG:append:pn-openvino-inference-engine = " python3"
+
+      # This adds OpenVINO related libraries in the target image.
+      CORE_IMAGE_EXTRA_INSTALL:append = " openvino-inference-engine"
+
+      # This adds OpenVINO samples in the target image.
+      CORE_IMAGE_EXTRA_INSTALL:append = " openvino-inference-engine-samples"
+
+      # Include OpenVINO Python API package in the target image.
+      CORE_IMAGE_EXTRA_INSTALL:append = " openvino-inference-engine-python3"
+
+```
+
+## Step 2: Build a Yocto Image with OpenVINO Packages
+
+Run BitBake to build your image with OpenVINO packages. For example, to build the minimal image, run the following command:
+
+
+```
+   bitbake core-image-minimal
+
+```
+
+## Step 3: Verify the Yocto Image
+
+Verify that OpenVINO packages were built successfully. Run the following command:
+
+```
+   oe-pkgdata-util list-pkgs | grep openvino
+
+```
+
+
+If the image build is successful, it will return the list of packages as below:
+
+```
+   openvino-inference-engine
+   openvino-inference-engine-dbg
+   openvino-inference-engine-dev
+   openvino-inference-engine-python3
+   openvino-inference-engine-samples
+   openvino-inference-engine-src
+   openvino-inference-engine-doc
+
+```

documentation/reporting_bugs.md

@@ -0,0 +1,22 @@
+## Reporting bugs
+
+If you have problems with or questions about a particular BSP, please
+contact the maintainer listed in the [Maintainer](../README.md#maintainers) section directly (cc:ing
+the Yocto mailing list puts it in the archive and helps other people
+who might have the same questions in the future), but please try to do
+the following first:
+
+- look in the [Yocto Project Bugzilla](http://bugzilla.yoctoproject.org/) to see if a
+  problem has already been reported
+
+- look through recent entries of the [meta-intel](https://lists.yoctoproject.org/g/meta-intel/messages)
+  and [Yocto Archives](https://lists.yoctoproject.org/g/yocto/messages) mailing list archives to see
+  if other people have run into similar problems or had similar questions answered.
+
+If you believe you have encountered a bug, you can open a new bug and
+enter the details in the [Yocto Project Bugzilla](https://bugzilla.yoctoproject.org/).
+If you're relatively certain that it's a bug against the BSP itself, please use the
+'BSPs | bsps-meta-intel' category for the bug; otherwise, please submit the bug against
+the most likely category for the problem. if you're wrong, it's not a big deal and
+the bug will be recategorized upon triage.
+

documentation/secureboot/README

@@ -1,38 +0,0 @@
-Currently, only one implementation of Secure Boot is available out of the box,
-which is using a single signed EFI application to directly boot the kernel with
-an optional initramfs.
-
-This can be added to your build either through local.conf, or via your own
-custom image recipe.
-
-If you are adding it via local.conf, set the following variables:
-
-IMAGE_FEATURES += "secureboot"
-WKS_FILE = "generic-bootdisk.wks.in"
-SECURE_BOOT_SIGNING_KEY = "/path/to/your/signing/key"
-SECURE_BOOT_SIGNING_CERT = "/path/to/your/signing/cert"
-IMAGE_CLASSES += "uefi-comboapp"
-
-If working with an image recipe, you can inherit uefi-comboapp directly instead
-of using the IMAGE_CLASSES variable.
-
-The signing keys and certs can be created via openssl commands. Here's an
-example:
-openssl req -new -x509 -newkey rsa:2048 -subj "/CN=your-subject/" -keyout \
-your-key.key -out your-key.crt -days 365 -nodes -sha256
-openssl x509 -in your-key.crt -out your-key.cer -outform DER
-
-The .crt file is your SECURE_BOOT_SIGNING_CERT, and the .key file is your
-SECURE_BOOT_SIGNING_KEY.
-
-You should enroll the .crt key in your firmware under the PK, KEK, and DB
-options (methods are different depending on your firmware). If a key should ever
-become invalid, enroll it under DBX to blacklist it.
-
-The comboapp can be further manipulated in a number of ways. You can modify the
-kernel command line via the APPEND variable, you can change the default UUID via
-the DISK_SIGNATURE_UUID variable, and you can modify the contents of the
-initramfs via the INITRD_IMAGE or INITRD_LIVE variables.
-
-A simple Secure Boot enabled image used for testing can be viewed at:
-common/recipes-selftest/images/secureboot-selftest-image-signed.bb

documentation/submitting_patches.md

@@ -0,0 +1,26 @@
+## Guidelines for submitting patches
+
+Please submit any patches against meta-intel BSPs to the
+[meta-intel mailing list](https://lists.yoctoproject.org/g/meta-intel)
+(email: meta-intel@lists.yoctoproject.org). Also, if your patches are
+available via a public git repository, please also include a URL to
+the repo and branch containing your patches as that makes it easier
+for maintainers to grab and test your patches.
+
+The patches should follow the suggestions outlined in the
+[Yocto Project and OpenEmbedded Contributor Guide](https://docs.yoctoproject.org/dev/contributor-guide/index.html).
+In addition, for any non-trivial patch, provide information about how you
+tested the patch, and for any non-trivial or non-obvious testing
+setup, provide details of that setup.
+
+Doing a quick 'git log' in meta-intel will provide you with many
+examples of good example commits if you have questions about any
+aspect of the preferred format.
+
+The meta-intel maintainers will do their best to review and/or pull in
+a patch or patch sets within 24 hours of the time it was posted.  For
+larger and/or more involved patches and patch sets, the review process
+may take longer.
+
+Please see the [maintainers](../README.md#maintainers) section for the list of maintainers. It's also
+a good idea to cc: the maintainer, if applicable.

documentation/tested_hardware.md

@@ -0,0 +1,21 @@
+## Tested Hardware
+
+The following undergo regular testing with their respective MACHINE types:
+
+- intel-corei7-64:
+    * Alder Lake-P/S/PS
+    * Amston Lake
+    * Elkhart Lake
+    * Metor Lake-P
+    * Raptor Lake-P/S
+    * Tiger Lake
+
+- intel-skylake-64:
+    * Alder Lake-P/S/PS
+    * Amston Lake
+    * Metor Lake-P
+    * Raptor Lake-P/S
+    * Tiger Lake
+
+- intel-core2-32:
+    * MinnowBoard Turbot

dynamic-layers/clang-layer/recipes-core/dnn/onednn_3.5.3.bb

@@ -3,7 +3,7 @@ SUMMARY  = "Deep Neural Network Library"
 DESCRIPTION = "This software is a user mode library that accelerates\
 deep-learning applications and frameworks on Intel architecture."
 LICENSE  = "Apache-2.0 & BSD-3-Clause & BSL-1.0"
-LIC_FILES_CHKSUM = "file://LICENSE;md5=b48e3de3bfd47c27882a0d85b20823f5 \
+LIC_FILES_CHKSUM = "file://LICENSE;md5=3b64000f6e7d52516017622a37a94ce9 \
                     file://tests/gtests/gtest/LICENSE;md5=cbbd27594afd089daa160d3a16dd515a \
                     file://src/cpu/x64/xbyak/COPYRIGHT;md5=3b9bf048d063d54cdb28964db558bcc7 \
                     file://src/common/ittnotify/LICENSE.BSD;md5=e671ff178b24a95a382ba670503c66fb \
@@ -12,9 +12,10 @@ SECTION = "lib"
 
 inherit pkgconfig cmake ptest
 
-S = "${WORKDIR}/git"
-SRCREV = "a08d38538efbc70e79ce138ce4ed31b982b5ce42"
-SRC_URI = "git://github.com/oneapi-src/oneDNN.git;branch=rls-v2.4 \
+DNN_BRANCH = "rls-v${@'.'.join(d.getVar('PV').split('.')[0:2])}"
+
+SRCREV = "66f0cb9eb66affd2da3bf5f8d897376f04aae6af"
+SRC_URI = "git://github.com/oneapi-src/oneDNN.git;branch=${DNN_BRANCH};protocol=https \
            file://run-ptest \
            "
 
@@ -32,10 +33,12 @@ EXTRA_OECMAKE += " \
                    -DDNNL_CPU_RUNTIME=OMP \
                    -DDNNL_ARCH_OPT_FLAGS="" \
                    -DCMAKE_SKIP_RPATH=ON \
+                   -DONEDNN_BUILD_GRAPH=OFF \
+                   -DCMAKE_POLICY_VERSION_MINIMUM=3.5 \
                    "
 
-PACKAGECONFIG ??= ""
-PACKAGECONFIG[gpu] = "-DDNNL_GPU_RUNTIME=OCL, , opencl-headers ocl-icd, intel-compute-runtime"
+PACKAGECONFIG ??= "gpu"
+PACKAGECONFIG[gpu] = "-DDNNL_GPU_RUNTIME=OCL, , opencl-headers virtual/opencl-icd, intel-compute-runtime"
 
 do_install:append () {
     install -d ${D}${bindir}/mkl-dnn/tests/benchdnn/inputs

dynamic-layers/clang-layer/recipes-core/ispc/ispc/0001-CMakeLists.txt-link-with-libclang-cpp-library-instea.patch

@@ -1,28 +0,0 @@
-From b9bc0df996d1e65fd70d5eb2d40866693f23bb67 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Thu, 24 Jun 2021 17:53:27 +0800
-Subject: [PATCH] CMakeLists.txt: link with libclang-cpp library instead
-
-Upstream-Status: Inappropriate
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- CMakeLists.txt | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index ef88317e..7507d6a5 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -281,7 +281,7 @@ if (WASM_ENABLED)
-     list(APPEND ISPC_TARGETS wasm-i32x4)
- endif()
- 
--set(CLANG_LIBRARY_LIST clangFrontend clangDriver clangSerialization clangParse clangSema clangAnalysis clangAST clangBasic clangEdit clangLex)
-+set(CLANG_LIBRARY_LIST clang-cpp)
- set(LLVM_COMPONENTS engine ipo bitreader bitwriter instrumentation linker option frontendopenmp)
- 
- if (X86_ENABLED)
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-core/ispc/ispc/8b5d0f26916e776bc3664e6a4dc68eff3a198d7a.patch

@@ -1,38 +0,0 @@
-From 8b5d0f26916e776bc3664e6a4dc68eff3a198d7a Mon Sep 17 00:00:00 2001
-From: Dmitry Babokin <dmitry.y.babokin@intel.com>
-Date: Wed, 16 Jun 2021 20:38:44 -0700
-Subject: [PATCH] Do not use depricated file open flags
-
-Upstream-Status: Backport [https://github.com/ispc/ispc/commit/8b5d0f26916e776bc3664e6a4dc68eff3a198d7a]
-Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
----
- src/module.cpp | 2 +-
- src/opt.cpp    | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/module.cpp b/src/module.cpp
-index 1e68d30c4..352bcd09e 100644
---- a/src/module.cpp
-+++ b/src/module.cpp
-@@ -1314,7 +1314,7 @@ bool Module::writeObjectFileOrAssembly(llvm::TargetMachine *targetMachine, llvm:
-     llvm::CodeGenFileType fileType = (outputType == Object) ? llvm::CGFT_ObjectFile : llvm::CGFT_AssemblyFile;
-     bool binary = (fileType == llvm::CGFT_ObjectFile);
- 
--    llvm::sys::fs::OpenFlags flags = binary ? llvm::sys::fs::F_None : llvm::sys::fs::F_Text;
-+    llvm::sys::fs::OpenFlags flags = binary ? llvm::sys::fs::OF_None : llvm::sys::fs::OF_Text;
- 
-     std::error_code error;
- 
-diff --git a/src/opt.cpp b/src/opt.cpp
-index ae1a11d3d..de1b27e1e 100644
---- a/src/opt.cpp
-+++ b/src/opt.cpp
-@@ -4687,7 +4687,7 @@ void DebugPassFile::run(llvm::Module &module, bool init) {
-     std::error_code EC;
-     char fname[100];
-     snprintf(fname, sizeof(fname), "%s_%d_%s.ll", init ? "init" : "ir", pnum, sanitize(std::string(pname)).c_str());
--    llvm::raw_fd_ostream OS(fname, EC, llvm::sys::fs::F_None);
-+    llvm::raw_fd_ostream OS(fname, EC, llvm::sys::fs::OF_None);
-     Assert(!EC && "IR dump file creation failed!");
-     module.print(OS, 0);
- }

dynamic-layers/clang-layer/recipes-core/ispc/ispc_1.16.1.bb

@@ -1,36 +0,0 @@
-SUMMARY  = "Intel(R) Implicit SPMD Program Compiler"
-DESCRIPTION = "ispc is a compiler for a variant of the C programming language, \
-with extensions for single program, multiple data programming."
-HOMEPAGE = "https://github.com/ispc/ispc"
-
-LICENSE  = "BSD-3-Clause & Apache-2.0-with-LLVM-exception"
-LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=da5ecffdd210b3cf776b32b41c182e87 \
-                    file://third-party-programs.txt;md5=3cd6f8a7c3bd9d2bb898fcb27c75221a"
-
-inherit cmake python3native
-
-S = "${WORKDIR}/git"
-
-SRC_URI = "git://github.com/ispc/ispc.git;protocol=https;branch=releases/v1.16.x \
-           file://0001-CMakeLists.txt-link-with-libclang-cpp-library-instea.patch \
-           file://0002-cmake-don-t-build-for-32-bit-targets.patch \
-           file://8b5d0f26916e776bc3664e6a4dc68eff3a198d7a.patch \
-           "
-SRCREV = "ae404c1da54422bc70696fbdaa4055bca0d1711e"
-
-COMPATIBLE_HOST = '(x86_64).*-linux'
-
-DEPENDS += " clang-native bison-native "
-RDEPENDS:${PN} += " clang-libllvm clang"
-
-EXTRA_OECMAKE += " \
-                  -DISPC_INCLUDE_TESTS=OFF  \
-                  -DISPC_INCLUDE_EXAMPLES=OFF  \
-                  -DISPC_NO_DUMPS=ON  \
-                  -DARM_ENABLED=OFF  \
-                  -DISPC_CROSS=ON  \
-                  -DSYSROOT_DIR=${STAGING_DIR_NATIVE}  \
-                  "
-
-TOOLCHAIN = "clang"
-BBCLASSEXTEND = "native nativesdk"

dynamic-layers/clang-layer/recipes-devtools/clang/files/BasicBlockUtils-Add-metadata-fixing-in-SplitBlockPre.patch

@@ -1,111 +0,0 @@
-From eeb816d95f0910bd246e37bb2bb3923acf0edf6b Mon Sep 17 00:00:00 2001
-From: Aleksander Us <aleksander.us@intel.com>
-Date: Mon, 26 Aug 2019 15:47:41 +0300
-Subject: [PATCH] [BasicBlockUtils] Add metadata fixing in
- SplitBlockPredecessors.
-
-In case when BB is header of some loop and predecessor is latch of
-this loop, metadata was not attached to newly created basic block.
-This led to loss of loop metadata for other passes.
-
-Upstream-Status: Submitted [https://reviews.llvm.org/D66892]
-
-https://github.com/intel/llvm-patches/commit/8af4449e2d201707f7f2f832b473a0439e255f32
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- lib/Transforms/Utils/BasicBlockUtils.cpp      | 23 ++++++++----
- test/Transforms/LoopSimplify/loop_metadata.ll | 36 +++++++++++++++++++
- 2 files changed, 52 insertions(+), 7 deletions(-)
- create mode 100644 test/Transforms/LoopSimplify/loop_metadata.ll
-
-diff --git a/lib/Transforms/Utils/BasicBlockUtils.cpp b/lib/Transforms/Utils/BasicBlockUtils.cpp
-index 5fa371377c8..3a90ae061fb 100644
---- a/lib/Transforms/Utils/BasicBlockUtils.cpp
-+++ b/lib/Transforms/Utils/BasicBlockUtils.cpp
-@@ -579,24 +579,33 @@ BasicBlock *llvm::SplitBlockPredecessors(BasicBlock *BB,
- 
-   // The new block unconditionally branches to the old block.
-   BranchInst *BI = BranchInst::Create(BB, NewBB);
-+  bool IsBBHeader = LI && LI->isLoopHeader(BB);
-+  Loop *BBLoop = LI ? LI->getLoopFor(BB) : nullptr;
-   // Splitting the predecessors of a loop header creates a preheader block.
--  if (LI && LI->isLoopHeader(BB))
-+  if (IsBBHeader)
-     // Using the loop start line number prevents debuggers stepping into the
-     // loop body for this instruction.
--    BI->setDebugLoc(LI->getLoopFor(BB)->getStartLoc());
-+    BI->setDebugLoc(BBLoop->getStartLoc());
-   else
-     BI->setDebugLoc(BB->getFirstNonPHIOrDbg()->getDebugLoc());
- 
-   // Move the edges from Preds to point to NewBB instead of BB.
--  for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
-+  for (BasicBlock *Pred : Preds) {
-+    Instruction *PI = Pred->getTerminator();
-     // This is slightly more strict than necessary; the minimum requirement
-     // is that there be no more than one indirectbr branching to BB. And
-     // all BlockAddress uses would need to be updated.
--    assert(!isa<IndirectBrInst>(Preds[i]->getTerminator()) &&
-+    assert(!isa<IndirectBrInst>(PI) &&
-            "Cannot split an edge from an IndirectBrInst");
--    assert(!isa<CallBrInst>(Preds[i]->getTerminator()) &&
--           "Cannot split an edge from a CallBrInst");
--    Preds[i]->getTerminator()->replaceUsesOfWith(BB, NewBB);
-+    assert(!isa<CallBrInst>(PI) && "Cannot split an edge from a CallBrInst");
-+    if (IsBBHeader && BBLoop->contains(Pred) && BBLoop->isLoopLatch(Pred)) {
-+      // Update loop metadata if it exists.
-+      if (MDNode *LoopMD = PI->getMetadata(LLVMContext::MD_loop)) {
-+        BI->setMetadata(LLVMContext::MD_loop, LoopMD);
-+        PI->setMetadata(LLVMContext::MD_loop, nullptr);
-+      }
-+    }
-+    PI->replaceUsesOfWith(BB, NewBB);
-   }
- 
-   // Insert a new PHI node into NewBB for every PHI node in BB and that new PHI
-diff --git a/test/Transforms/LoopSimplify/loop_metadata.ll b/test/Transforms/LoopSimplify/loop_metadata.ll
-new file mode 100644
-index 00000000000..c15c92fe3ae
---- /dev/null
-+++ b/test/Transforms/LoopSimplify/loop_metadata.ll
-@@ -0,0 +1,36 @@
-+; RUN: opt -S -loop-simplify < %s | FileCheck %s
-+
-+; CHECK: for.cond.loopexit:
-+; CHECK: br label %for.cond, !llvm.loop !0
-+; CHECK: br i1 %cmp1, label %for.body1, label %for.cond.loopexit
-+
-+define void @foo() {
-+entry:
-+  br label %for.cond
-+
-+for.cond:                                         ; preds = %for.cond1, %entry
-+  %j = phi i32 [ 0, %entry ], [ %add, %for.cond1 ]
-+  %cmp = icmp ult i32 %j, 8
-+  br i1 %cmp, label %for.body, label %for.end
-+
-+for.body:                                         ; preds = %for.cond
-+  %dummy1 = add i32 1, 1
-+  %add = add nuw nsw i32 %j, 1
-+  br label %for.cond1
-+
-+for.cond1:                                      ; preds = %for.body1, %for.body
-+  %i.0 = phi i32 [ 1, %for.body ], [ %inc, %for.body1 ]
-+  %cmp1 = icmp ult i32 %i.0, 8
-+  br i1 %cmp1, label %for.body1, label %for.cond, !llvm.loop !0
-+
-+for.body1:                                      ; preds = %for.cond1
-+  %dummy2 = add i32 1, 1
-+  %inc = add nuw nsw i32 %i.0, 1
-+  br label %for.cond1
-+
-+for.end:                                       ; preds = %for.cond
-+  ret void
-+}
-+
-+!0 = distinct !{!0, !1}
-+!1 = !{!"llvm.loop.unroll.full"}
--- 
-2.18.0
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/IndVarSimplify-Do-not-use-SCEV-expander-for-IVCount-.patch

@@ -1,146 +0,0 @@
-From 35e218a886f4c066eabd18685240d55270bd5a6d Mon Sep 17 00:00:00 2001
-From: Aleksander Us <aleksander.us@intel.com>
-Date: Mon, 26 Aug 2019 15:45:47 +0300
-Subject: [PATCH] [IndVarSimplify] Do not use SCEV expander for IVCount in
- LFTR when possible.
-
-SCEV analysis cannot properly cache instruction with poison flags
-(for example, add nsw outside of loop will not be reused by expander).
-This can lead to generating of additional instructions by SCEV expander.
-
-Example IR:
-
-  ...
-  %maxval = add nuw nsw i32 %a1, %a2
-  ...
-for.body:
-  ...
-  %cmp22 = icmp ult i32 %ivadd, %maxval
-  br i1 %cmp22, label %for.body, label %for.end
-  ...
-
-SCEV expander will generate copy of %maxval in preheader but without
-nuw/nsw flags. This can be avoided by explicit check that iv count
-value gives the same SCEV expressions as calculated by LFTR.
-
-Upstream-Status: Submitted [https://reviews.llvm.org/D66890]
-
-https://github.com/intel/llvm-patches/commit/fd6a6c97341a56fd21bc32bc940afea751312e8f
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- lib/Transforms/Scalar/IndVarSimplify.cpp     | 12 +++++++++-
- test/Transforms/IndVarSimplify/add_nsw.ll    | 23 ++++++++++++++++++++
- test/Transforms/IndVarSimplify/lftr-reuse.ll |  9 +++-----
- test/Transforms/IndVarSimplify/udiv.ll       |  1 +
- 4 files changed, 38 insertions(+), 7 deletions(-)
- create mode 100644 test/Transforms/IndVarSimplify/add_nsw.ll
-
-diff --git a/lib/Transforms/Scalar/IndVarSimplify.cpp b/lib/Transforms/Scalar/IndVarSimplify.cpp
-index f9fc698a4a9..5e04dac8aa6 100644
---- a/lib/Transforms/Scalar/IndVarSimplify.cpp
-+++ b/lib/Transforms/Scalar/IndVarSimplify.cpp
-@@ -2375,6 +2375,17 @@ static Value *genLoopLimit(PHINode *IndVar, BasicBlock *ExitingBB,
-     if (UsePostInc)
-       IVLimit = SE->getAddExpr(IVLimit, SE->getOne(IVLimit->getType()));
- 
-+    // If computed limit is equal to old limit then do not use SCEV expander
-+    // because it can lost NUW/NSW flags and create extra instructions.
-+    BranchInst *BI = cast<BranchInst>(ExitingBB->getTerminator());
-+    if (ICmpInst *Cmp = dyn_cast<ICmpInst>(BI->getOperand(0))) {
-+      Value *Limit = Cmp->getOperand(0);
-+      if (!L->isLoopInvariant(Limit))
-+        Limit = Cmp->getOperand(1);
-+      if (SE->getSCEV(Limit) == IVLimit)
-+        return Limit;
-+    }
-+
-     // Expand the code for the iteration count.
-     assert(SE->isLoopInvariant(IVLimit, L) &&
-            "Computed iteration count is not loop invariant!");
-@@ -2383,7 +2394,6 @@ static Value *genLoopLimit(PHINode *IndVar, BasicBlock *ExitingBB,
-     // SCEV expression (IVInit) for a pointer type IV value (IndVar).
-     Type *LimitTy = ExitCount->getType()->isPointerTy() ?
-       IndVar->getType() : ExitCount->getType();
--    BranchInst *BI = cast<BranchInst>(ExitingBB->getTerminator());
-     return Rewriter.expandCodeFor(IVLimit, LimitTy, BI);
-   }
- }
-diff --git a/test/Transforms/IndVarSimplify/add_nsw.ll b/test/Transforms/IndVarSimplify/add_nsw.ll
-new file mode 100644
-index 00000000000..abd1cbb6c51
---- /dev/null
-+++ b/test/Transforms/IndVarSimplify/add_nsw.ll
-@@ -0,0 +1,23 @@
-+; RUN: opt -indvars -S %s | FileCheck %s
-+
-+target datalayout = "e-p:32:32-i64:64-n8:16:32"
-+
-+; CHECK: for.body.preheader:
-+; CHECK-NOT: add
-+; CHECK: for.body:
-+
-+define void @foo(i32 %a1, i32 %a2) {
-+entry:
-+  %maxval = add nuw nsw i32 %a1, %a2
-+  %cmp = icmp slt i32 %maxval, 1
-+  br i1 %cmp, label %for.end, label %for.body
-+
-+for.body:                                         ; preds = %entry, %for.body
-+  %j.02 = phi i32 [ 0, %entry ], [ %add31, %for.body ]
-+  %add31 = add nuw nsw i32 %j.02, 1
-+  %cmp22 = icmp slt i32 %add31, %maxval
-+  br i1 %cmp22, label %for.body, label %for.end
-+
-+for.end:                                          ; preds = %for.body
-+  ret void
-+}
-diff --git a/test/Transforms/IndVarSimplify/lftr-reuse.ll b/test/Transforms/IndVarSimplify/lftr-reuse.ll
-index 14ae9738696..509d662b767 100644
---- a/test/Transforms/IndVarSimplify/lftr-reuse.ll
-+++ b/test/Transforms/IndVarSimplify/lftr-reuse.ll
-@@ -67,11 +67,9 @@ define void @expandOuterRecurrence(i32 %arg) nounwind {
- ; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 0, [[SUB1]]
- ; CHECK-NEXT:    br i1 [[CMP1]], label [[OUTER_PREHEADER:%.*]], label [[EXIT:%.*]]
- ; CHECK:       outer.preheader:
--; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[ARG]], -1
- ; CHECK-NEXT:    br label [[OUTER:%.*]]
- ; CHECK:       outer:
--; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i32 [ [[TMP0]], [[OUTER_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[OUTER_INC:%.*]] ]
--; CHECK-NEXT:    [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC]] ], [ 0, [[OUTER_PREHEADER]] ]
-+; CHECK-NEXT:    [[I:%.*]] = phi i32 [ [[I_INC:%.*]], [[OUTER_INC:%.*]] ], [ 0, [[OUTER_PREHEADER]] ]
- ; CHECK-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
- ; CHECK-NEXT:    [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
- ; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 0, [[SUB3]]
-@@ -81,14 +79,13 @@ define void @expandOuterRecurrence(i32 %arg) nounwind {
- ; CHECK:       inner:
- ; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[INNER_PH]] ], [ [[J_INC:%.*]], [[INNER]] ]
- ; CHECK-NEXT:    [[J_INC]] = add nuw nsw i32 [[J]], 1
--; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i32 [[J_INC]], [[INDVARS_IV]]
-+; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i32 [[J_INC]], [[SUB3]]
- ; CHECK-NEXT:    br i1 [[EXITCOND]], label [[INNER]], label [[OUTER_INC_LOOPEXIT:%.*]]
- ; CHECK:       outer.inc.loopexit:
- ; CHECK-NEXT:    br label [[OUTER_INC]]
- ; CHECK:       outer.inc:
- ; CHECK-NEXT:    [[I_INC]] = add nuw nsw i32 [[I]], 1
--; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], -1
--; CHECK-NEXT:    [[EXITCOND1:%.*]] = icmp ne i32 [[I_INC]], [[TMP0]]
-+; CHECK-NEXT:    [[EXITCOND1:%.*]] = icmp ne i32 [[I_INC]], [[SUB1]]
- ; CHECK-NEXT:    br i1 [[EXITCOND1]], label [[OUTER]], label [[EXIT_LOOPEXIT:%.*]]
- ; CHECK:       exit.loopexit:
- ; CHECK-NEXT:    br label [[EXIT]]
-diff --git a/test/Transforms/IndVarSimplify/udiv.ll b/test/Transforms/IndVarSimplify/udiv.ll
-index b3f2c2a6a66..3530343ef4a 100644
---- a/test/Transforms/IndVarSimplify/udiv.ll
-+++ b/test/Transforms/IndVarSimplify/udiv.ll
-@@ -133,6 +133,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind
- ; CHECK-LABEL: @foo(
- ; CHECK: for.body.preheader:
- ; CHECK-NOT: udiv
-+; CHECK: for.body:
- 
- define void @foo(double* %p, i64 %n) nounwind {
- entry:
--- 
-2.18.0
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0001-llvm-spirv-skip-building-tests.patch

@@ -1,51 +0,0 @@
-From 661021749a168c423d69d0ba7cdfa16fed860836 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Wed, 21 Aug 2019 14:35:31 +0800
-Subject: [PATCH 1/3] llvm-spirv: skip building tests
-
-Some of these need clang to be built and since we're building this in-tree,
-that leads to problems when compiling libcxx, compiler-rt which aren't built
-in-tree.
-
-Instead of using SPIRV_SKIP_CLANG_BUILD to skip clang build and adding this to
-all components, disable the building of tests altogether.
-
-Upstream-Status: Inappropriate
-
-Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- CMakeLists.txt | 10 ----------
- 1 file changed, 10 deletions(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index 92c50370..80999c98 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -25,13 +25,6 @@ if(LLVM_SPIRV_BUILD_EXTERNAL)
-   set(CMAKE_CXX_STANDARD 14)
-   set(CMAKE_CXX_STANDARD_REQUIRED ON)
- 
--  if(LLVM_SPIRV_INCLUDE_TESTS)
--    set(LLVM_TEST_COMPONENTS
--      llvm-as
--      llvm-dis
--    )
--  endif(LLVM_SPIRV_INCLUDE_TESTS)
--
-   find_package(LLVM 10.0.0 REQUIRED
-     COMPONENTS
-       Analysis
-@@ -63,9 +56,6 @@ set(LLVM_SPIRV_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/include)
- 
- add_subdirectory(lib/SPIRV)
- add_subdirectory(tools/llvm-spirv)
--if(LLVM_SPIRV_INCLUDE_TESTS)
--  add_subdirectory(test)
--endif(LLVM_SPIRV_INCLUDE_TESTS)
- 
- install(
-   FILES
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0002-Add-cl_khr_extended_subgroup-extensions.patch

@@ -1,812 +0,0 @@
-From 3f544cfe44ee5f113a3fb554aca2cf5d64996062 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Wed, 7 Apr 2021 16:38:38 +0800
-Subject: [PATCH 2/7] Add cl_khr_extended_subgroup extensions.
-
-Added extensions and their function declarations into
-the standard header.
-
-Patch by Piotr Fusik!
-
-Tags: #clang
-
-Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/4a4402f0d72167477a6252e4c3daf5089ebc8f9a]
-Signed-off-by: Anastasia Stulova <anastasia.stulova@arm.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- .../include/clang/Basic/OpenCLExtensions.def  |   7 +
- clang/lib/Headers/opencl-c.h                  | 668 ++++++++++++++++++
- clang/test/SemaOpenCL/extension-version.cl    |  83 +++
- 3 files changed, 758 insertions(+)
-
-diff --git a/clang/include/clang/Basic/OpenCLExtensions.def b/clang/include/clang/Basic/OpenCLExtensions.def
-index 608f78a13eef..d1574164f9b2 100644
---- a/clang/include/clang/Basic/OpenCLExtensions.def
-+++ b/clang/include/clang/Basic/OpenCLExtensions.def
-@@ -74,6 +74,13 @@ OPENCLEXT_INTERNAL(cl_khr_mipmap_image_writes, 200, ~0U)
- OPENCLEXT_INTERNAL(cl_khr_srgb_image_writes, 200, ~0U)
- OPENCLEXT_INTERNAL(cl_khr_subgroups, 200, ~0U)
- OPENCLEXT_INTERNAL(cl_khr_terminate_context, 200, ~0U)
-+OPENCLEXT_INTERNAL(cl_khr_subgroup_extended_types, 200, ~0U)
-+OPENCLEXT_INTERNAL(cl_khr_subgroup_non_uniform_vote, 200, ~0U)
-+OPENCLEXT_INTERNAL(cl_khr_subgroup_ballot, 200, ~0U)
-+OPENCLEXT_INTERNAL(cl_khr_subgroup_non_uniform_arithmetic, 200, ~0U)
-+OPENCLEXT_INTERNAL(cl_khr_subgroup_shuffle, 200, ~0U)
-+OPENCLEXT_INTERNAL(cl_khr_subgroup_shuffle_relative, 200, ~0U)
-+OPENCLEXT_INTERNAL(cl_khr_subgroup_clustered_reduce, 200, ~0U)
- 
- // Clang Extensions.
- OPENCLEXT_INTERNAL(cl_clang_storage_class_specifiers, 100, ~0U)
-diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h
-index 93a946cec5b1..67d900eb1c3d 100644
---- a/clang/lib/Headers/opencl-c.h
-+++ b/clang/lib/Headers/opencl-c.h
-@@ -17530,6 +17530,674 @@ double  __ovld __conv sub_group_scan_inclusive_max(double x);
- 
- #endif //cl_khr_subgroups cl_intel_subgroups
- 
-+#if defined(cl_khr_subgroup_extended_types)
-+char __ovld __conv sub_group_broadcast( char value, uint index );
-+char2 __ovld __conv sub_group_broadcast( char2 value, uint index );
-+char3 __ovld __conv sub_group_broadcast( char3 value, uint index );
-+char4 __ovld __conv sub_group_broadcast( char4 value, uint index );
-+char8 __ovld __conv sub_group_broadcast( char8 value, uint index );
-+char16 __ovld __conv sub_group_broadcast( char16 value, uint index );
-+
-+uchar __ovld __conv sub_group_broadcast( uchar value, uint index );
-+uchar2 __ovld __conv sub_group_broadcast( uchar2 value, uint index );
-+uchar3 __ovld __conv sub_group_broadcast( uchar3 value, uint index );
-+uchar4 __ovld __conv sub_group_broadcast( uchar4 value, uint index );
-+uchar8 __ovld __conv sub_group_broadcast( uchar8 value, uint index );
-+uchar16 __ovld __conv sub_group_broadcast( uchar16 value, uint index );
-+
-+short __ovld __conv sub_group_broadcast( short value, uint index );
-+short2 __ovld __conv sub_group_broadcast( short2 value, uint index );
-+short3 __ovld __conv sub_group_broadcast( short3 value, uint index );
-+short4 __ovld __conv sub_group_broadcast( short4 value, uint index );
-+short8 __ovld __conv sub_group_broadcast( short8 value, uint index );
-+short16 __ovld __conv sub_group_broadcast( short16 value, uint index );
-+
-+ushort __ovld __conv sub_group_broadcast( ushort value, uint index );
-+ushort2 __ovld __conv sub_group_broadcast( ushort2 value, uint index );
-+ushort3 __ovld __conv sub_group_broadcast( ushort3 value, uint index );
-+ushort4 __ovld __conv sub_group_broadcast( ushort4 value, uint index );
-+ushort8 __ovld __conv sub_group_broadcast( ushort8 value, uint index );
-+ushort16 __ovld __conv sub_group_broadcast( ushort16 value, uint index );
-+
-+// scalar int broadcast is part of cl_khr_subgroups
-+int2 __ovld __conv sub_group_broadcast( int2 value, uint index );
-+int3 __ovld __conv sub_group_broadcast( int3 value, uint index );
-+int4 __ovld __conv sub_group_broadcast( int4 value, uint index );
-+int8 __ovld __conv sub_group_broadcast( int8 value, uint index );
-+int16 __ovld __conv sub_group_broadcast( int16 value, uint index );
-+
-+// scalar uint broadcast is part of cl_khr_subgroups
-+uint2 __ovld __conv sub_group_broadcast( uint2 value, uint index );
-+uint3 __ovld __conv sub_group_broadcast( uint3 value, uint index );
-+uint4 __ovld __conv sub_group_broadcast( uint4 value, uint index );
-+uint8 __ovld __conv sub_group_broadcast( uint8 value, uint index );
-+uint16 __ovld __conv sub_group_broadcast( uint16 value, uint index );
-+
-+// scalar long broadcast is part of cl_khr_subgroups
-+long2 __ovld __conv sub_group_broadcast( long2 value, uint index );
-+long3 __ovld __conv sub_group_broadcast( long3 value, uint index );
-+long4 __ovld __conv sub_group_broadcast( long4 value, uint index );
-+long8 __ovld __conv sub_group_broadcast( long8 value, uint index );
-+long16 __ovld __conv sub_group_broadcast( long16 value, uint index );
-+
-+// scalar ulong broadcast is part of cl_khr_subgroups
-+ulong2 __ovld __conv sub_group_broadcast( ulong2 value, uint index );
-+ulong3 __ovld __conv sub_group_broadcast( ulong3 value, uint index );
-+ulong4 __ovld __conv sub_group_broadcast( ulong4 value, uint index );
-+ulong8 __ovld __conv sub_group_broadcast( ulong8 value, uint index );
-+ulong16 __ovld __conv sub_group_broadcast( ulong16 value, uint index );
-+
-+// scalar float broadcast is part of cl_khr_subgroups
-+float2 __ovld __conv sub_group_broadcast( float2 value, uint index );
-+float3 __ovld __conv sub_group_broadcast( float3 value, uint index );
-+float4 __ovld __conv sub_group_broadcast( float4 value, uint index );
-+float8 __ovld __conv sub_group_broadcast( float8 value, uint index );
-+float16 __ovld __conv sub_group_broadcast( float16 value, uint index );
-+
-+char __ovld __conv sub_group_reduce_add( char value );
-+uchar __ovld __conv sub_group_reduce_add( uchar value );
-+short __ovld __conv sub_group_reduce_add( short value );
-+ushort __ovld __conv sub_group_reduce_add( ushort value );
-+
-+char __ovld __conv sub_group_reduce_min( char value );
-+uchar __ovld __conv sub_group_reduce_min( uchar value );
-+short __ovld __conv sub_group_reduce_min( short value );
-+ushort __ovld __conv sub_group_reduce_min( ushort value );
-+
-+char __ovld __conv sub_group_reduce_max( char value );
-+uchar __ovld __conv sub_group_reduce_max( uchar value );
-+short __ovld __conv sub_group_reduce_max( short value );
-+ushort __ovld __conv sub_group_reduce_max( ushort value );
-+
-+char __ovld __conv sub_group_scan_inclusive_add( char value );
-+uchar __ovld __conv sub_group_scan_inclusive_add( uchar value );
-+short __ovld __conv sub_group_scan_inclusive_add( short value );
-+ushort __ovld __conv sub_group_scan_inclusive_add( ushort value );
-+
-+char __ovld __conv sub_group_scan_inclusive_min( char value );
-+uchar __ovld __conv sub_group_scan_inclusive_min( uchar value );
-+short __ovld __conv sub_group_scan_inclusive_min( short value );
-+ushort __ovld __conv sub_group_scan_inclusive_min( ushort value );
-+
-+char __ovld __conv sub_group_scan_inclusive_max( char value );
-+uchar __ovld __conv sub_group_scan_inclusive_max( uchar value );
-+short __ovld __conv sub_group_scan_inclusive_max( short value );
-+ushort __ovld __conv sub_group_scan_inclusive_max( ushort value );
-+
-+char __ovld __conv sub_group_scan_exclusive_add( char value );
-+uchar __ovld __conv sub_group_scan_exclusive_add( uchar value );
-+short __ovld __conv sub_group_scan_exclusive_add( short value );
-+ushort __ovld __conv sub_group_scan_exclusive_add( ushort value );
-+
-+char __ovld __conv sub_group_scan_exclusive_min( char value );
-+uchar __ovld __conv sub_group_scan_exclusive_min( uchar value );
-+short __ovld __conv sub_group_scan_exclusive_min( short value );
-+ushort __ovld __conv sub_group_scan_exclusive_min( ushort value );
-+
-+char __ovld __conv sub_group_scan_exclusive_max( char value );
-+uchar __ovld __conv sub_group_scan_exclusive_max( uchar value );
-+short __ovld __conv sub_group_scan_exclusive_max( short value );
-+ushort __ovld __conv sub_group_scan_exclusive_max( ushort value );
-+
-+#if defined(cl_khr_fp16)
-+// scalar half broadcast is part of cl_khr_subgroups
-+half2 __ovld __conv sub_group_broadcast( half2 value, uint index );
-+half3 __ovld __conv sub_group_broadcast( half3 value, uint index );
-+half4 __ovld __conv sub_group_broadcast( half4 value, uint index );
-+half8 __ovld __conv sub_group_broadcast( half8 value, uint index );
-+half16 __ovld __conv sub_group_broadcast( half16 value, uint index );
-+#endif  // cl_khr_fp16
-+
-+#if defined(cl_khr_fp64)
-+// scalar double broadcast is part of cl_khr_subgroups
-+double2 __ovld __conv sub_group_broadcast( double2 value, uint index );
-+double3 __ovld __conv sub_group_broadcast( double3 value, uint index );
-+double4 __ovld __conv sub_group_broadcast( double4 value, uint index );
-+double8 __ovld __conv sub_group_broadcast( double8 value, uint index );
-+double16 __ovld __conv sub_group_broadcast( double16 value, uint index );
-+#endif  // cl_khr_fp64
-+
-+#endif  // cl_khr_subgroup_extended_types
-+
-+#if defined(cl_khr_subgroup_non_uniform_vote)
-+int     __ovld sub_group_elect(void);
-+int     __ovld sub_group_non_uniform_all( int predicate );
-+int     __ovld sub_group_non_uniform_any( int predicate );
-+
-+int     __ovld sub_group_non_uniform_all_equal( char value );
-+int     __ovld sub_group_non_uniform_all_equal( uchar value );
-+int     __ovld sub_group_non_uniform_all_equal( short value );
-+int     __ovld sub_group_non_uniform_all_equal( ushort value );
-+int     __ovld sub_group_non_uniform_all_equal( int value );
-+int     __ovld sub_group_non_uniform_all_equal( uint value );
-+int     __ovld sub_group_non_uniform_all_equal( long value );
-+int     __ovld sub_group_non_uniform_all_equal( ulong value );
-+int     __ovld sub_group_non_uniform_all_equal( float value );
-+
-+#if defined(cl_khr_fp16)
-+int     __ovld sub_group_non_uniform_all_equal( half value );
-+#endif // cl_khr_fp16
-+
-+#if defined(cl_khr_fp64)
-+int     __ovld sub_group_non_uniform_all_equal( double value );
-+#endif // cl_khr_fp64
-+
-+#endif // cl_khr_subgroup_non_uniform_vote
-+
-+#if defined(cl_khr_subgroup_ballot)
-+char    __ovld sub_group_non_uniform_broadcast( char value, uint index );
-+char2   __ovld sub_group_non_uniform_broadcast( char2 value, uint index );
-+char3   __ovld sub_group_non_uniform_broadcast( char3 value, uint index );
-+char4   __ovld sub_group_non_uniform_broadcast( char4 value, uint index );
-+char8   __ovld sub_group_non_uniform_broadcast( char8 value, uint index );
-+char16  __ovld sub_group_non_uniform_broadcast( char16 value, uint index );
-+
-+uchar   __ovld sub_group_non_uniform_broadcast( uchar value, uint index );
-+uchar2  __ovld sub_group_non_uniform_broadcast( uchar2 value, uint index );
-+uchar3  __ovld sub_group_non_uniform_broadcast( uchar3 value, uint index );
-+uchar4  __ovld sub_group_non_uniform_broadcast( uchar4 value, uint index );
-+uchar8  __ovld sub_group_non_uniform_broadcast( uchar8 value, uint index );
-+uchar16 __ovld sub_group_non_uniform_broadcast( uchar16 value, uint index );
-+
-+short   __ovld sub_group_non_uniform_broadcast( short value, uint index );
-+short2  __ovld sub_group_non_uniform_broadcast( short2 value, uint index );
-+short3  __ovld sub_group_non_uniform_broadcast( short3 value, uint index );
-+short4  __ovld sub_group_non_uniform_broadcast( short4 value, uint index );
-+short8  __ovld sub_group_non_uniform_broadcast( short8 value, uint index );
-+short16 __ovld sub_group_non_uniform_broadcast( short16 value, uint index );
-+
-+ushort  __ovld sub_group_non_uniform_broadcast( ushort value, uint index );
-+ushort2 __ovld sub_group_non_uniform_broadcast( ushort2 value, uint index );
-+ushort3 __ovld sub_group_non_uniform_broadcast( ushort3 value, uint index );
-+ushort4 __ovld sub_group_non_uniform_broadcast( ushort4 value, uint index );
-+ushort8 __ovld sub_group_non_uniform_broadcast( ushort8 value, uint index );
-+ushort16 __ovld sub_group_non_uniform_broadcast( ushort16 value, uint index );
-+
-+int     __ovld sub_group_non_uniform_broadcast( int value, uint index );
-+int2    __ovld sub_group_non_uniform_broadcast( int2 value, uint index );
-+int3    __ovld sub_group_non_uniform_broadcast( int3 value, uint index );
-+int4    __ovld sub_group_non_uniform_broadcast( int4 value, uint index );
-+int8    __ovld sub_group_non_uniform_broadcast( int8 value, uint index );
-+int16   __ovld sub_group_non_uniform_broadcast( int16 value, uint index );
-+
-+uint    __ovld sub_group_non_uniform_broadcast( uint value, uint index );
-+uint2   __ovld sub_group_non_uniform_broadcast( uint2 value, uint index );
-+uint3   __ovld sub_group_non_uniform_broadcast( uint3 value, uint index );
-+uint4   __ovld sub_group_non_uniform_broadcast( uint4 value, uint index );
-+uint8   __ovld sub_group_non_uniform_broadcast( uint8 value, uint index );
-+uint16  __ovld sub_group_non_uniform_broadcast( uint16 value, uint index );
-+
-+long    __ovld sub_group_non_uniform_broadcast( long value, uint index );
-+long2   __ovld sub_group_non_uniform_broadcast( long2 value, uint index );
-+long3   __ovld sub_group_non_uniform_broadcast( long3 value, uint index );
-+long4   __ovld sub_group_non_uniform_broadcast( long4 value, uint index );
-+long8   __ovld sub_group_non_uniform_broadcast( long8 value, uint index );
-+long16  __ovld sub_group_non_uniform_broadcast( long16 value, uint index );
-+
-+ulong   __ovld sub_group_non_uniform_broadcast( ulong value, uint index );
-+ulong2  __ovld sub_group_non_uniform_broadcast( ulong2 value, uint index );
-+ulong3  __ovld sub_group_non_uniform_broadcast( ulong3 value, uint index );
-+ulong4  __ovld sub_group_non_uniform_broadcast( ulong4 value, uint index );
-+ulong8  __ovld sub_group_non_uniform_broadcast( ulong8 value, uint index );
-+ulong16 __ovld sub_group_non_uniform_broadcast( ulong16 value, uint index );
-+
-+float   __ovld sub_group_non_uniform_broadcast( float value, uint index );
-+float2  __ovld sub_group_non_uniform_broadcast( float2 value, uint index );
-+float3  __ovld sub_group_non_uniform_broadcast( float3 value, uint index );
-+float4  __ovld sub_group_non_uniform_broadcast( float4 value, uint index );
-+float8  __ovld sub_group_non_uniform_broadcast( float8 value, uint index );
-+float16 __ovld sub_group_non_uniform_broadcast( float16 value, uint index );
-+
-+char    __ovld sub_group_broadcast_first( char value );
-+uchar   __ovld sub_group_broadcast_first( uchar value );
-+short   __ovld sub_group_broadcast_first( short value );
-+ushort  __ovld sub_group_broadcast_first( ushort value );
-+int     __ovld sub_group_broadcast_first( int value );
-+uint    __ovld sub_group_broadcast_first( uint value );
-+long    __ovld sub_group_broadcast_first( long value );
-+ulong   __ovld sub_group_broadcast_first( ulong value );
-+float   __ovld sub_group_broadcast_first( float value );
-+
-+uint4   __ovld sub_group_ballot( int predicate );
-+int     __ovld __cnfn sub_group_inverse_ballot( uint4 value );
-+int     __ovld __cnfn sub_group_ballot_bit_extract( uint4 value, uint index );
-+uint    __ovld __cnfn sub_group_ballot_bit_count( uint4 value );
-+
-+uint    __ovld sub_group_ballot_inclusive_scan( uint4 value );
-+uint    __ovld sub_group_ballot_exclusive_scan( uint4 value );
-+uint    __ovld sub_group_ballot_find_lsb( uint4 value );
-+uint    __ovld sub_group_ballot_find_msb( uint4 value );
-+
-+uint4   __ovld __cnfn get_sub_group_eq_mask(void);
-+uint4   __ovld __cnfn get_sub_group_ge_mask(void);
-+uint4   __ovld __cnfn get_sub_group_gt_mask(void);
-+uint4   __ovld __cnfn get_sub_group_le_mask(void);
-+uint4   __ovld __cnfn get_sub_group_lt_mask(void);
-+
-+#if defined(cl_khr_fp16)
-+half    __ovld sub_group_non_uniform_broadcast( half value, uint index );
-+half2   __ovld sub_group_non_uniform_broadcast( half2 value, uint index );
-+half3   __ovld sub_group_non_uniform_broadcast( half3 value, uint index );
-+half4   __ovld sub_group_non_uniform_broadcast( half4 value, uint index );
-+half8   __ovld sub_group_non_uniform_broadcast( half8 value, uint index );
-+half16  __ovld sub_group_non_uniform_broadcast( half16 value, uint index );
-+
-+half    __ovld sub_group_broadcast_first( half value );
-+#endif // cl_khr_fp16
-+
-+#if defined(cl_khr_fp64)
-+double   __ovld sub_group_non_uniform_broadcast( double value, uint index );
-+double2  __ovld sub_group_non_uniform_broadcast( double2 value, uint index );
-+double3  __ovld sub_group_non_uniform_broadcast( double3 value, uint index );
-+double4  __ovld sub_group_non_uniform_broadcast( double4 value, uint index );
-+double8  __ovld sub_group_non_uniform_broadcast( double8 value, uint index );
-+double16 __ovld sub_group_non_uniform_broadcast( double16 value, uint index );
-+
-+double   __ovld sub_group_broadcast_first( double value );
-+#endif // cl_khr_fp64
-+
-+#endif // cl_khr_subgroup_ballot
-+
-+#if defined(cl_khr_subgroup_non_uniform_arithmetic)
-+char    __ovld sub_group_non_uniform_reduce_add( char value );
-+uchar   __ovld sub_group_non_uniform_reduce_add( uchar value );
-+short   __ovld sub_group_non_uniform_reduce_add( short value );
-+ushort  __ovld sub_group_non_uniform_reduce_add( ushort value );
-+int     __ovld sub_group_non_uniform_reduce_add( int value );
-+uint    __ovld sub_group_non_uniform_reduce_add( uint value );
-+long    __ovld sub_group_non_uniform_reduce_add( long value );
-+ulong   __ovld sub_group_non_uniform_reduce_add( ulong value );
-+float   __ovld sub_group_non_uniform_reduce_add( float value );
-+
-+char    __ovld sub_group_non_uniform_reduce_mul( char value );
-+uchar   __ovld sub_group_non_uniform_reduce_mul( uchar value );
-+short   __ovld sub_group_non_uniform_reduce_mul( short value );
-+ushort  __ovld sub_group_non_uniform_reduce_mul( ushort value );
-+int     __ovld sub_group_non_uniform_reduce_mul( int value );
-+uint    __ovld sub_group_non_uniform_reduce_mul( uint value );
-+long    __ovld sub_group_non_uniform_reduce_mul( long value );
-+ulong   __ovld sub_group_non_uniform_reduce_mul( ulong value );
-+float   __ovld sub_group_non_uniform_reduce_mul( float value );
-+
-+char    __ovld sub_group_non_uniform_reduce_min( char value );
-+uchar   __ovld sub_group_non_uniform_reduce_min( uchar value );
-+short   __ovld sub_group_non_uniform_reduce_min( short value );
-+ushort  __ovld sub_group_non_uniform_reduce_min( ushort value );
-+int     __ovld sub_group_non_uniform_reduce_min( int value );
-+uint    __ovld sub_group_non_uniform_reduce_min( uint value );
-+long    __ovld sub_group_non_uniform_reduce_min( long value );
-+ulong   __ovld sub_group_non_uniform_reduce_min( ulong value );
-+float   __ovld sub_group_non_uniform_reduce_min( float value );
-+
-+char    __ovld sub_group_non_uniform_reduce_max( char value );
-+uchar   __ovld sub_group_non_uniform_reduce_max( uchar value );
-+short   __ovld sub_group_non_uniform_reduce_max( short value );
-+ushort  __ovld sub_group_non_uniform_reduce_max( ushort value );
-+int     __ovld sub_group_non_uniform_reduce_max( int value );
-+uint    __ovld sub_group_non_uniform_reduce_max( uint value );
-+long    __ovld sub_group_non_uniform_reduce_max( long value );
-+ulong   __ovld sub_group_non_uniform_reduce_max( ulong value );
-+float   __ovld sub_group_non_uniform_reduce_max( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_inclusive_add( char value );
-+uchar   __ovld sub_group_non_uniform_scan_inclusive_add( uchar value );
-+short   __ovld sub_group_non_uniform_scan_inclusive_add( short value );
-+ushort  __ovld sub_group_non_uniform_scan_inclusive_add( ushort value );
-+int     __ovld sub_group_non_uniform_scan_inclusive_add( int value );
-+uint    __ovld sub_group_non_uniform_scan_inclusive_add( uint value );
-+long    __ovld sub_group_non_uniform_scan_inclusive_add( long value );
-+ulong   __ovld sub_group_non_uniform_scan_inclusive_add( ulong value );
-+float   __ovld sub_group_non_uniform_scan_inclusive_add( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_inclusive_mul( char value );
-+uchar   __ovld sub_group_non_uniform_scan_inclusive_mul( uchar value );
-+short   __ovld sub_group_non_uniform_scan_inclusive_mul( short value );
-+ushort  __ovld sub_group_non_uniform_scan_inclusive_mul( ushort value );
-+int     __ovld sub_group_non_uniform_scan_inclusive_mul( int value );
-+uint    __ovld sub_group_non_uniform_scan_inclusive_mul( uint value );
-+long    __ovld sub_group_non_uniform_scan_inclusive_mul( long value );
-+ulong   __ovld sub_group_non_uniform_scan_inclusive_mul( ulong value );
-+float   __ovld sub_group_non_uniform_scan_inclusive_mul( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_inclusive_min( char value );
-+uchar   __ovld sub_group_non_uniform_scan_inclusive_min( uchar value );
-+short   __ovld sub_group_non_uniform_scan_inclusive_min( short value );
-+ushort  __ovld sub_group_non_uniform_scan_inclusive_min( ushort value );
-+int     __ovld sub_group_non_uniform_scan_inclusive_min( int value );
-+uint    __ovld sub_group_non_uniform_scan_inclusive_min( uint value );
-+long    __ovld sub_group_non_uniform_scan_inclusive_min( long value );
-+ulong   __ovld sub_group_non_uniform_scan_inclusive_min( ulong value );
-+float   __ovld sub_group_non_uniform_scan_inclusive_min( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_inclusive_max( char value );
-+uchar   __ovld sub_group_non_uniform_scan_inclusive_max( uchar value );
-+short   __ovld sub_group_non_uniform_scan_inclusive_max( short value );
-+ushort  __ovld sub_group_non_uniform_scan_inclusive_max( ushort value );
-+int     __ovld sub_group_non_uniform_scan_inclusive_max( int value );
-+uint    __ovld sub_group_non_uniform_scan_inclusive_max( uint value );
-+long    __ovld sub_group_non_uniform_scan_inclusive_max( long value );
-+ulong   __ovld sub_group_non_uniform_scan_inclusive_max( ulong value );
-+float   __ovld sub_group_non_uniform_scan_inclusive_max( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_exclusive_add( char value );
-+uchar   __ovld sub_group_non_uniform_scan_exclusive_add( uchar value );
-+short   __ovld sub_group_non_uniform_scan_exclusive_add( short value );
-+ushort  __ovld sub_group_non_uniform_scan_exclusive_add( ushort value );
-+int     __ovld sub_group_non_uniform_scan_exclusive_add( int value );
-+uint    __ovld sub_group_non_uniform_scan_exclusive_add( uint value );
-+long    __ovld sub_group_non_uniform_scan_exclusive_add( long value );
-+ulong   __ovld sub_group_non_uniform_scan_exclusive_add( ulong value );
-+float   __ovld sub_group_non_uniform_scan_exclusive_add( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_exclusive_mul( char value );
-+uchar   __ovld sub_group_non_uniform_scan_exclusive_mul( uchar value );
-+short   __ovld sub_group_non_uniform_scan_exclusive_mul( short value );
-+ushort  __ovld sub_group_non_uniform_scan_exclusive_mul( ushort value );
-+int     __ovld sub_group_non_uniform_scan_exclusive_mul( int value );
-+uint    __ovld sub_group_non_uniform_scan_exclusive_mul( uint value );
-+long    __ovld sub_group_non_uniform_scan_exclusive_mul( long value );
-+ulong   __ovld sub_group_non_uniform_scan_exclusive_mul( ulong value );
-+float   __ovld sub_group_non_uniform_scan_exclusive_mul( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_exclusive_min( char value );
-+uchar   __ovld sub_group_non_uniform_scan_exclusive_min( uchar value );
-+short   __ovld sub_group_non_uniform_scan_exclusive_min( short value );
-+ushort  __ovld sub_group_non_uniform_scan_exclusive_min( ushort value );
-+int     __ovld sub_group_non_uniform_scan_exclusive_min( int value );
-+uint    __ovld sub_group_non_uniform_scan_exclusive_min( uint value );
-+long    __ovld sub_group_non_uniform_scan_exclusive_min( long value );
-+ulong   __ovld sub_group_non_uniform_scan_exclusive_min( ulong value );
-+float   __ovld sub_group_non_uniform_scan_exclusive_min( float value );
-+
-+char    __ovld sub_group_non_uniform_scan_exclusive_max( char value );
-+uchar   __ovld sub_group_non_uniform_scan_exclusive_max( uchar value );
-+short   __ovld sub_group_non_uniform_scan_exclusive_max( short value );
-+ushort  __ovld sub_group_non_uniform_scan_exclusive_max( ushort value );
-+int     __ovld sub_group_non_uniform_scan_exclusive_max( int value );
-+uint    __ovld sub_group_non_uniform_scan_exclusive_max( uint value );
-+long    __ovld sub_group_non_uniform_scan_exclusive_max( long value );
-+ulong   __ovld sub_group_non_uniform_scan_exclusive_max( ulong value );
-+float   __ovld sub_group_non_uniform_scan_exclusive_max( float value );
-+
-+char    __ovld sub_group_non_uniform_reduce_and( char value );
-+uchar   __ovld sub_group_non_uniform_reduce_and( uchar value );
-+short   __ovld sub_group_non_uniform_reduce_and( short value );
-+ushort  __ovld sub_group_non_uniform_reduce_and( ushort value );
-+int     __ovld sub_group_non_uniform_reduce_and( int value );
-+uint    __ovld sub_group_non_uniform_reduce_and( uint value );
-+long    __ovld sub_group_non_uniform_reduce_and( long value );
-+ulong   __ovld sub_group_non_uniform_reduce_and( ulong value );
-+
-+char    __ovld sub_group_non_uniform_reduce_or( char value );
-+uchar   __ovld sub_group_non_uniform_reduce_or( uchar value );
-+short   __ovld sub_group_non_uniform_reduce_or( short value );
-+ushort  __ovld sub_group_non_uniform_reduce_or( ushort value );
-+int     __ovld sub_group_non_uniform_reduce_or( int value );
-+uint    __ovld sub_group_non_uniform_reduce_or( uint value );
-+long    __ovld sub_group_non_uniform_reduce_or( long value );
-+ulong   __ovld sub_group_non_uniform_reduce_or( ulong value );
-+
-+char    __ovld sub_group_non_uniform_reduce_xor( char value );
-+uchar   __ovld sub_group_non_uniform_reduce_xor( uchar value );
-+short   __ovld sub_group_non_uniform_reduce_xor( short value );
-+ushort  __ovld sub_group_non_uniform_reduce_xor( ushort value );
-+int     __ovld sub_group_non_uniform_reduce_xor( int value );
-+uint    __ovld sub_group_non_uniform_reduce_xor( uint value );
-+long    __ovld sub_group_non_uniform_reduce_xor( long value );
-+ulong   __ovld sub_group_non_uniform_reduce_xor( ulong value );
-+
-+char    __ovld sub_group_non_uniform_scan_inclusive_and( char value );
-+uchar   __ovld sub_group_non_uniform_scan_inclusive_and( uchar value );
-+short   __ovld sub_group_non_uniform_scan_inclusive_and( short value );
-+ushort  __ovld sub_group_non_uniform_scan_inclusive_and( ushort value );
-+int     __ovld sub_group_non_uniform_scan_inclusive_and( int value );
-+uint    __ovld sub_group_non_uniform_scan_inclusive_and( uint value );
-+long    __ovld sub_group_non_uniform_scan_inclusive_and( long value );
-+ulong   __ovld sub_group_non_uniform_scan_inclusive_and( ulong value );
-+
-+char    __ovld sub_group_non_uniform_scan_inclusive_or( char value );
-+uchar   __ovld sub_group_non_uniform_scan_inclusive_or( uchar value );
-+short   __ovld sub_group_non_uniform_scan_inclusive_or( short value );
-+ushort  __ovld sub_group_non_uniform_scan_inclusive_or( ushort value );
-+int     __ovld sub_group_non_uniform_scan_inclusive_or( int value );
-+uint    __ovld sub_group_non_uniform_scan_inclusive_or( uint value );
-+long    __ovld sub_group_non_uniform_scan_inclusive_or( long value );
-+ulong   __ovld sub_group_non_uniform_scan_inclusive_or( ulong value );
-+
-+char    __ovld sub_group_non_uniform_scan_inclusive_xor( char value );
-+uchar   __ovld sub_group_non_uniform_scan_inclusive_xor( uchar value );
-+short   __ovld sub_group_non_uniform_scan_inclusive_xor( short value );
-+ushort  __ovld sub_group_non_uniform_scan_inclusive_xor( ushort value );
-+int     __ovld sub_group_non_uniform_scan_inclusive_xor( int value );
-+uint    __ovld sub_group_non_uniform_scan_inclusive_xor( uint value );
-+long    __ovld sub_group_non_uniform_scan_inclusive_xor( long value );
-+ulong   __ovld sub_group_non_uniform_scan_inclusive_xor( ulong value );
-+
-+char    __ovld sub_group_non_uniform_scan_exclusive_and( char value );
-+uchar   __ovld sub_group_non_uniform_scan_exclusive_and( uchar value );
-+short   __ovld sub_group_non_uniform_scan_exclusive_and( short value );
-+ushort  __ovld sub_group_non_uniform_scan_exclusive_and( ushort value );
-+int     __ovld sub_group_non_uniform_scan_exclusive_and( int value );
-+uint    __ovld sub_group_non_uniform_scan_exclusive_and( uint value );
-+long    __ovld sub_group_non_uniform_scan_exclusive_and( long value );
-+ulong   __ovld sub_group_non_uniform_scan_exclusive_and( ulong value );
-+
-+char    __ovld sub_group_non_uniform_scan_exclusive_or( char value );
-+uchar   __ovld sub_group_non_uniform_scan_exclusive_or( uchar value );
-+short   __ovld sub_group_non_uniform_scan_exclusive_or( short value );
-+ushort  __ovld sub_group_non_uniform_scan_exclusive_or( ushort value );
-+int     __ovld sub_group_non_uniform_scan_exclusive_or( int value );
-+uint    __ovld sub_group_non_uniform_scan_exclusive_or( uint value );
-+long    __ovld sub_group_non_uniform_scan_exclusive_or( long value );
-+ulong   __ovld sub_group_non_uniform_scan_exclusive_or( ulong value );
-+
-+char    __ovld sub_group_non_uniform_scan_exclusive_xor( char value );
-+uchar   __ovld sub_group_non_uniform_scan_exclusive_xor( uchar value );
-+short   __ovld sub_group_non_uniform_scan_exclusive_xor( short value );
-+ushort  __ovld sub_group_non_uniform_scan_exclusive_xor( ushort value );
-+int     __ovld sub_group_non_uniform_scan_exclusive_xor( int value );
-+uint    __ovld sub_group_non_uniform_scan_exclusive_xor( uint value );
-+long    __ovld sub_group_non_uniform_scan_exclusive_xor( long value );
-+ulong   __ovld sub_group_non_uniform_scan_exclusive_xor( ulong value );
-+
-+int     __ovld sub_group_non_uniform_reduce_logical_and( int predicate );
-+int     __ovld sub_group_non_uniform_reduce_logical_or( int predicate );
-+int     __ovld sub_group_non_uniform_reduce_logical_xor( int predicate );
-+
-+int     __ovld sub_group_non_uniform_scan_inclusive_logical_and( int predicate );
-+int     __ovld sub_group_non_uniform_scan_inclusive_logical_or( int predicate );
-+int     __ovld sub_group_non_uniform_scan_inclusive_logical_xor( int predicate );
-+
-+int     __ovld sub_group_non_uniform_scan_exclusive_logical_and( int predicate );
-+int     __ovld sub_group_non_uniform_scan_exclusive_logical_or( int predicate );
-+int     __ovld sub_group_non_uniform_scan_exclusive_logical_xor( int predicate );
-+
-+#if defined(cl_khr_fp16)
-+half    __ovld sub_group_non_uniform_reduce_add( half value );
-+half    __ovld sub_group_non_uniform_reduce_mul( half value );
-+half    __ovld sub_group_non_uniform_reduce_min( half value );
-+half    __ovld sub_group_non_uniform_reduce_max( half value );
-+half    __ovld sub_group_non_uniform_scan_inclusive_add( half value );
-+half    __ovld sub_group_non_uniform_scan_inclusive_mul( half value );
-+half    __ovld sub_group_non_uniform_scan_inclusive_min( half value );
-+half    __ovld sub_group_non_uniform_scan_inclusive_max( half value );
-+half    __ovld sub_group_non_uniform_scan_exclusive_add( half value );
-+half    __ovld sub_group_non_uniform_scan_exclusive_mul( half value );
-+half    __ovld sub_group_non_uniform_scan_exclusive_min( half value );
-+half    __ovld sub_group_non_uniform_scan_exclusive_max( half value );
-+#endif // cl_khr_fp16
-+
-+#if defined(cl_khr_fp64)
-+double  __ovld sub_group_non_uniform_reduce_add( double value );
-+double  __ovld sub_group_non_uniform_reduce_mul( double value );
-+double  __ovld sub_group_non_uniform_reduce_min( double value );
-+double  __ovld sub_group_non_uniform_reduce_max( double value );
-+double  __ovld sub_group_non_uniform_scan_inclusive_add( double value );
-+double  __ovld sub_group_non_uniform_scan_inclusive_mul( double value );
-+double  __ovld sub_group_non_uniform_scan_inclusive_min( double value );
-+double  __ovld sub_group_non_uniform_scan_inclusive_max( double value );
-+double  __ovld sub_group_non_uniform_scan_exclusive_add( double value );
-+double  __ovld sub_group_non_uniform_scan_exclusive_mul( double value );
-+double  __ovld sub_group_non_uniform_scan_exclusive_min( double value );
-+double  __ovld sub_group_non_uniform_scan_exclusive_max( double value );
-+#endif // cl_khr_fp64
-+
-+#endif // cl_khr_subgroup_non_uniform_arithmetic
-+
-+#if defined(cl_khr_subgroup_shuffle)
-+char    __ovld sub_group_shuffle( char value, uint index );
-+uchar   __ovld sub_group_shuffle( uchar value, uint index );
-+short   __ovld sub_group_shuffle( short value, uint index );
-+ushort  __ovld sub_group_shuffle( ushort value, uint index );
-+int     __ovld sub_group_shuffle( int value, uint index );
-+uint    __ovld sub_group_shuffle( uint value, uint index );
-+long    __ovld sub_group_shuffle( long value, uint index );
-+ulong   __ovld sub_group_shuffle( ulong value, uint index );
-+float   __ovld sub_group_shuffle( float value, uint index );
-+
-+char    __ovld sub_group_shuffle_xor( char value, uint mask );
-+uchar   __ovld sub_group_shuffle_xor( uchar value, uint mask );
-+short   __ovld sub_group_shuffle_xor( short value, uint mask );
-+ushort  __ovld sub_group_shuffle_xor( ushort value, uint mask );
-+int     __ovld sub_group_shuffle_xor( int value, uint mask );
-+uint    __ovld sub_group_shuffle_xor( uint value, uint mask );
-+long    __ovld sub_group_shuffle_xor( long value, uint mask );
-+ulong   __ovld sub_group_shuffle_xor( ulong value, uint mask );
-+float   __ovld sub_group_shuffle_xor( float value, uint mask );
-+
-+#if defined(cl_khr_fp16)
-+half    __ovld sub_group_shuffle( half value, uint index );
-+half    __ovld sub_group_shuffle_xor( half value, uint mask );
-+#endif // cl_khr_fp16
-+
-+#if defined(cl_khr_fp64)
-+double  __ovld sub_group_shuffle( double value, uint index );
-+double  __ovld sub_group_shuffle_xor( double value, uint mask );
-+#endif // cl_khr_fp64
-+
-+#endif // cl_khr_subgroup_shuffle
-+
-+#if defined(cl_khr_subgroup_shuffle_relative)
-+char    __ovld sub_group_shuffle_up( char value, uint delta );
-+uchar   __ovld sub_group_shuffle_up( uchar value, uint delta );
-+short   __ovld sub_group_shuffle_up( short value, uint delta );
-+ushort  __ovld sub_group_shuffle_up( ushort value, uint delta );
-+int     __ovld sub_group_shuffle_up( int value, uint delta );
-+uint    __ovld sub_group_shuffle_up( uint value, uint delta );
-+long    __ovld sub_group_shuffle_up( long value, uint delta );
-+ulong   __ovld sub_group_shuffle_up( ulong value, uint delta );
-+float   __ovld sub_group_shuffle_up( float value, uint delta );
-+
-+char    __ovld sub_group_shuffle_down( char value, uint delta );
-+uchar   __ovld sub_group_shuffle_down( uchar value, uint delta );
-+short   __ovld sub_group_shuffle_down( short value, uint delta );
-+ushort  __ovld sub_group_shuffle_down( ushort value, uint delta );
-+int     __ovld sub_group_shuffle_down( int value, uint delta );
-+uint    __ovld sub_group_shuffle_down( uint value, uint delta );
-+long    __ovld sub_group_shuffle_down( long value, uint delta );
-+ulong   __ovld sub_group_shuffle_down( ulong value, uint delta );
-+float   __ovld sub_group_shuffle_down( float value, uint delta );
-+
-+#if defined(cl_khr_fp16)
-+half    __ovld sub_group_shuffle_up( half value, uint delta );
-+half    __ovld sub_group_shuffle_down( half value, uint delta );
-+#endif // cl_khr_fp16
-+
-+#if defined(cl_khr_fp64)
-+double  __ovld sub_group_shuffle_up( double value, uint delta );
-+double  __ovld sub_group_shuffle_down( double value, uint delta );
-+#endif // cl_khr_fp64
-+
-+#endif // cl_khr_subgroup_shuffle_relative
-+
-+#if defined(cl_khr_subgroup_clustered_reduce)
-+char    __ovld sub_group_clustered_reduce_add( char value, uint clustersize );
-+uchar   __ovld sub_group_clustered_reduce_add( uchar value, uint clustersize );
-+short   __ovld sub_group_clustered_reduce_add( short value, uint clustersize );
-+ushort  __ovld sub_group_clustered_reduce_add( ushort value, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_add( int value, uint clustersize );
-+uint    __ovld sub_group_clustered_reduce_add( uint value, uint clustersize );
-+long    __ovld sub_group_clustered_reduce_add( long value, uint clustersize );
-+ulong   __ovld sub_group_clustered_reduce_add( ulong value, uint clustersize );
-+float   __ovld sub_group_clustered_reduce_add( float value, uint clustersize );
-+
-+char    __ovld sub_group_clustered_reduce_mul( char value, uint clustersize );
-+uchar   __ovld sub_group_clustered_reduce_mul( uchar value, uint clustersize );
-+short   __ovld sub_group_clustered_reduce_mul( short value, uint clustersize );
-+ushort  __ovld sub_group_clustered_reduce_mul( ushort value, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_mul( int value, uint clustersize );
-+uint    __ovld sub_group_clustered_reduce_mul( uint value, uint clustersize );
-+long    __ovld sub_group_clustered_reduce_mul( long value, uint clustersize );
-+ulong   __ovld sub_group_clustered_reduce_mul( ulong value, uint clustersize );
-+float   __ovld sub_group_clustered_reduce_mul( float value, uint clustersize );
-+
-+char    __ovld sub_group_clustered_reduce_min( char value, uint clustersize );
-+uchar   __ovld sub_group_clustered_reduce_min( uchar value, uint clustersize );
-+short   __ovld sub_group_clustered_reduce_min( short value, uint clustersize );
-+ushort  __ovld sub_group_clustered_reduce_min( ushort value, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_min( int value, uint clustersize );
-+uint    __ovld sub_group_clustered_reduce_min( uint value, uint clustersize );
-+long    __ovld sub_group_clustered_reduce_min( long value, uint clustersize );
-+ulong   __ovld sub_group_clustered_reduce_min( ulong value, uint clustersize );
-+float   __ovld sub_group_clustered_reduce_min( float value, uint clustersize );
-+
-+char    __ovld sub_group_clustered_reduce_max( char value, uint clustersize );
-+uchar   __ovld sub_group_clustered_reduce_max( uchar value, uint clustersize );
-+short   __ovld sub_group_clustered_reduce_max( short value, uint clustersize );
-+ushort  __ovld sub_group_clustered_reduce_max( ushort value, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_max( int value, uint clustersize );
-+uint    __ovld sub_group_clustered_reduce_max( uint value, uint clustersize );
-+long    __ovld sub_group_clustered_reduce_max( long value, uint clustersize );
-+ulong   __ovld sub_group_clustered_reduce_max( ulong value, uint clustersize );
-+float   __ovld sub_group_clustered_reduce_max( float value, uint clustersize );
-+
-+char    __ovld sub_group_clustered_reduce_and( char value, uint clustersize );
-+uchar   __ovld sub_group_clustered_reduce_and( uchar value, uint clustersize );
-+short   __ovld sub_group_clustered_reduce_and( short value, uint clustersize );
-+ushort  __ovld sub_group_clustered_reduce_and( ushort value, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_and( int value, uint clustersize );
-+uint    __ovld sub_group_clustered_reduce_and( uint value, uint clustersize );
-+long    __ovld sub_group_clustered_reduce_and( long value, uint clustersize );
-+ulong   __ovld sub_group_clustered_reduce_and( ulong value, uint clustersize );
-+
-+char    __ovld sub_group_clustered_reduce_or( char value, uint clustersize );
-+uchar   __ovld sub_group_clustered_reduce_or( uchar value, uint clustersize );
-+short   __ovld sub_group_clustered_reduce_or( short value, uint clustersize );
-+ushort  __ovld sub_group_clustered_reduce_or( ushort value, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_or( int value, uint clustersize );
-+uint    __ovld sub_group_clustered_reduce_or( uint value, uint clustersize );
-+long    __ovld sub_group_clustered_reduce_or( long value, uint clustersize );
-+ulong   __ovld sub_group_clustered_reduce_or( ulong value, uint clustersize );
-+
-+char    __ovld sub_group_clustered_reduce_xor( char value, uint clustersize );
-+uchar   __ovld sub_group_clustered_reduce_xor( uchar value, uint clustersize );
-+short   __ovld sub_group_clustered_reduce_xor( short value, uint clustersize );
-+ushort  __ovld sub_group_clustered_reduce_xor( ushort value, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_xor( int value, uint clustersize );
-+uint    __ovld sub_group_clustered_reduce_xor( uint value, uint clustersize );
-+long    __ovld sub_group_clustered_reduce_xor( long value, uint clustersize );
-+ulong   __ovld sub_group_clustered_reduce_xor( ulong value, uint clustersize );
-+
-+int     __ovld sub_group_clustered_reduce_logical_and( int predicate, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_logical_or( int predicate, uint clustersize );
-+int     __ovld sub_group_clustered_reduce_logical_xor( int predicate, uint clustersize );
-+
-+#if defined(cl_khr_fp16)
-+half    __ovld sub_group_clustered_reduce_add( half value, uint clustersize );
-+half    __ovld sub_group_clustered_reduce_mul( half value, uint clustersize );
-+half    __ovld sub_group_clustered_reduce_min( half value, uint clustersize );
-+half    __ovld sub_group_clustered_reduce_max( half value, uint clustersize );
-+#endif // cl_khr_fp16
-+
-+#if defined(cl_khr_fp64)
-+double  __ovld sub_group_clustered_reduce_add( double value, uint clustersize );
-+double  __ovld sub_group_clustered_reduce_mul( double value, uint clustersize );
-+double  __ovld sub_group_clustered_reduce_min( double value, uint clustersize );
-+double  __ovld sub_group_clustered_reduce_max( double value, uint clustersize );
-+#endif // cl_khr_fp64
-+
-+#endif // cl_khr_subgroup_clustered_reduce
-+
- #if defined(cl_intel_subgroups)
- // Intel-Specific Sub Group Functions
- float   __ovld __conv intel_sub_group_shuffle( float  x, uint c );
-diff --git a/clang/test/SemaOpenCL/extension-version.cl b/clang/test/SemaOpenCL/extension-version.cl
-index 0e6bbb7d3bcd..86c78143a0eb 100644
---- a/clang/test/SemaOpenCL/extension-version.cl
-+++ b/clang/test/SemaOpenCL/extension-version.cl
-@@ -333,3 +333,86 @@
- #endif
- #pragma OPENCL EXTENSION cl_intel_device_side_avc_motion_estimation : enable
- 
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+#ifndef cl_khr_subgroup_extended_types
-+#error "Missing cl_khr_subgroup_extended_types"
-+#endif
-+#else
-+#ifdef cl_khr_subgroup_extended_types
-+#error "Incorrect cl_khr_subgroup_extended_types define"
-+#endif
-+// expected-warning@+2{{unsupported OpenCL extension 'cl_khr_subgroup_extended_types' - ignoring}}
-+#endif
-+#pragma OPENCL EXTENSION cl_khr_subgroup_extended_types : enable
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+#ifndef cl_khr_subgroup_non_uniform_vote
-+#error "Missing cl_khr_subgroup_non_uniform_vote"
-+#endif
-+#else
-+#ifdef cl_khr_subgroup_non_uniform_vote
-+#error "Incorrect cl_khr_subgroup_non_uniform_vote define"
-+#endif
-+// expected-warning@+2{{unsupported OpenCL extension 'cl_khr_subgroup_non_uniform_vote' - ignoring}}
-+#endif
-+#pragma OPENCL EXTENSION cl_khr_subgroup_non_uniform_vote : enable
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+#ifndef cl_khr_subgroup_ballot
-+#error "Missing cl_khr_subgroup_ballot"
-+#endif
-+#else
-+#ifdef cl_khr_subgroup_ballot
-+#error "Incorrect cl_khr_subgroup_ballot define"
-+#endif
-+// expected-warning@+2{{unsupported OpenCL extension 'cl_khr_subgroup_ballot' - ignoring}}
-+#endif
-+#pragma OPENCL EXTENSION cl_khr_subgroup_ballot : enable
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+#ifndef cl_khr_subgroup_non_uniform_arithmetic
-+#error "Missing cl_khr_subgroup_non_uniform_arithmetic"
-+#endif
-+#else
-+#ifdef cl_khr_subgroup_non_uniform_arithmetic
-+#error "Incorrect cl_khr_subgroup_non_uniform_arithmetic define"
-+#endif
-+// expected-warning@+2{{unsupported OpenCL extension 'cl_khr_subgroup_non_uniform_arithmetic' - ignoring}}
-+#endif
-+#pragma OPENCL EXTENSION cl_khr_subgroup_non_uniform_arithmetic : enable
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+#ifndef cl_khr_subgroup_shuffle
-+#error "Missing cl_khr_subgroup_shuffle"
-+#endif
-+#else
-+#ifdef cl_khr_subgroup_shuffle
-+#error "Incorrect cl_khr_subgroup_shuffle define"
-+#endif
-+// expected-warning@+2{{unsupported OpenCL extension 'cl_khr_subgroup_shuffle' - ignoring}}
-+#endif
-+#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+#ifndef cl_khr_subgroup_shuffle_relative
-+#error "Missing cl_khr_subgroup_shuffle_relative"
-+#endif
-+#else
-+#ifdef cl_khr_subgroup_shuffle_relative
-+#error "Incorrect cl_khr_subgroup_shuffle_relative define"
-+#endif
-+// expected-warning@+2{{unsupported OpenCL extension 'cl_khr_subgroup_shuffle_relative' - ignoring}}
-+#endif
-+#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle_relative : enable
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+#ifndef cl_khr_subgroup_clustered_reduce
-+#error "Missing cl_khr_subgroup_clustered_reduce"
-+#endif
-+#else
-+#ifdef cl_khr_subgroup_clustered_reduce
-+#error "Incorrect cl_khr_subgroup_clustered_reduce define"
-+#endif
-+// expected-warning@+2{{unsupported OpenCL extension 'cl_khr_subgroup_clustered_reduce' - ignoring}}
-+#endif
-+#pragma OPENCL EXTENSION cl_khr_subgroup_clustered_reduce : enable
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0002-Fix-building-in-tree-with-cmake-DLLVM_LINK_LLVM_DYLI.patch

@@ -1,33 +0,0 @@
-From 331e323ae2633a8999a660314022491d670c442c Mon Sep 17 00:00:00 2001
-From: Andrea Bocci <andrea.bocci@cern.ch>
-Date: Sun, 15 Mar 2020 17:35:44 +0100
-Subject: [PATCH 2/3] Fix building in-tree with cmake -DLLVM_LINK_LLVM_DYLIB=ON
-
-Building in-tree with LLVM 11.0 master with the LLVM_LINK_LLVM_DYLIB
-cmake flag fails to link with the LLVMSPIRVLib library.
-
-Add an explicit dependency to force the correct build order and linking.
-
-Signed-off-by: Andrea Bocci <andrea.bocci@cern.ch>
-Upstream-Status: Backport
-Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
----
- tools/llvm-spirv/CMakeLists.txt | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/tools/llvm-spirv/CMakeLists.txt b/tools/llvm-spirv/CMakeLists.txt
-index 9aa96d9c..501c0daf 100644
---- a/tools/llvm-spirv/CMakeLists.txt
-+++ b/tools/llvm-spirv/CMakeLists.txt
-@@ -14,7 +14,7 @@ add_llvm_tool(llvm-spirv
-   NO_INSTALL_RPATH
- )
- 
--if (LLVM_SPIRV_BUILD_EXTERNAL)
-+if (LLVM_SPIRV_BUILD_EXTERNAL OR LLVM_LINK_LLVM_DYLIB)
-   target_link_libraries(llvm-spirv PRIVATE LLVMSPIRVLib)
- endif()
- 
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0003-Add-support-for-cl_ext_float_atomics-in-SPIRVWriter.patch

@@ -1,982 +0,0 @@
-From fbc9996d6490a5d4720b85b47f38335e7fdc99d9 Mon Sep 17 00:00:00 2001
-From: haonanya <haonan.yang@intel.com>
-Date: Mon, 19 Jul 2021 10:14:20 +0800
-Subject: [PATCH 3/3] Add support for cl_ext_float_atomics in SPIRVWriter
-
-Upstream-Status: Backport [Taken from opencl-clang patches, https://github.com/intel/opencl-clang/blob/ocl-open-100/patches/spirv/0001-Add-support-for-cl_ext_float_atomics-in-SPIRVWriter.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- lib/SPIRV/OCL20ToSPIRV.cpp            |  79 ++++++++++++++++--
- lib/SPIRV/SPIRVToOCL.h                |   3 +
- lib/SPIRV/SPIRVToOCL12.cpp            |  21 +++++
- lib/SPIRV/SPIRVToOCL20.cpp            |  28 ++++++-
- lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h |   1 -
- lib/SPIRV/libSPIRV/SPIRVOpCode.h      |   8 +-
- test/AtomicFAddEXTForOCL.ll           |  64 +++++++++++++++
- test/AtomicFAddExt.ll                 | 111 ++++++++-----------------
- test/AtomicFMaxEXT.ll                 | 113 +++++++-------------------
- test/AtomicFMaxEXTForOCL.ll           |  64 +++++++++++++++
- test/AtomicFMinEXT.ll                 | 113 +++++++-------------------
- test/AtomicFMinEXTForOCL.ll           |  64 +++++++++++++++
- test/InvalidAtomicBuiltins.cl         |   8 --
- 13 files changed, 417 insertions(+), 260 deletions(-)
- create mode 100644 test/AtomicFAddEXTForOCL.ll
- create mode 100644 test/AtomicFMaxEXTForOCL.ll
- create mode 100644 test/AtomicFMinEXTForOCL.ll
-
-diff --git a/lib/SPIRV/OCL20ToSPIRV.cpp b/lib/SPIRV/OCL20ToSPIRV.cpp
-index e30aa5be..b676a009 100644
---- a/lib/SPIRV/OCL20ToSPIRV.cpp
-+++ b/lib/SPIRV/OCL20ToSPIRV.cpp
-@@ -408,10 +408,63 @@ void OCL20ToSPIRV::visitCallInst(CallInst &CI) {
-   if (DemangledName.find(kOCLBuiltinName::AtomicPrefix) == 0 ||
-       DemangledName.find(kOCLBuiltinName::AtomPrefix) == 0) {
- 
--    // Compute atomic builtins do not support floating types.
--    if (CI.getType()->isFloatingPointTy() &&
--        isComputeAtomicOCLBuiltin(DemangledName))
--      return;
-+    // Compute "atom" prefixed builtins do not support floating types.
-+    if (CI.getType()->isFloatingPointTy()) {
-+      if (DemangledName.find(kOCLBuiltinName::AtomPrefix) == 0)
-+        return;
-+      // handle functions which are "atomic_" prefixed.
-+      StringRef Stem = DemangledName;
-+      Stem = Stem.drop_front(strlen("atomic_"));
-+      // FP-typed atomic_{add, sub, inc, dec, exchange, min, max, or, and, xor,
-+      // fetch_or, fetch_xor, fetch_and, fetch_or_explicit, fetch_xor_explicit,
-+      // fetch_and_explicit} should be identified as function call
-+      bool IsFunctionCall = llvm::StringSwitch<bool>(Stem)
-+                                .Case("add", true)
-+                                .Case("sub", true)
-+                                .Case("inc", true)
-+                                .Case("dec", true)
-+                                .Case("cmpxchg", true)
-+                                .Case("min", true)
-+                                .Case("max", true)
-+                                .Case("or", true)
-+                                .Case("xor", true)
-+                                .Case("and", true)
-+                                .Case("fetch_or", true)
-+                                .Case("fetch_and", true)
-+                                .Case("fetch_xor", true)
-+                                .Case("fetch_or_explicit", true)
-+                                .Case("fetch_xor_explicit", true)
-+                                .Case("fetch_and_explicit", true)
-+                                .Default(false);
-+      if (IsFunctionCall)
-+        return;
-+      if (F->arg_size() != 2) {
-+        IsFunctionCall = llvm::StringSwitch<bool>(Stem)
-+                             .Case("exchange", true)
-+                             .Case("fetch_add", true)
-+                             .Case("fetch_sub", true)
-+                             .Case("fetch_min", true)
-+                             .Case("fetch_max", true)
-+                             .Case("load", true)
-+                             .Case("store", true)
-+                             .Default(false);
-+        if (IsFunctionCall)
-+          return;
-+      }
-+      if (F->arg_size() != 3 && F->arg_size() != 4) {
-+        IsFunctionCall = llvm::StringSwitch<bool>(Stem)
-+                             .Case("exchange_explicit", true)
-+                             .Case("fetch_add_explicit", true)
-+                             .Case("fetch_sub_explicit", true)
-+                             .Case("fetch_min_explicit", true)
-+                             .Case("fetch_max_explicit", true)
-+                             .Case("load_explicit", true)
-+                             .Case("store_explicit", true)
-+                             .Default(false);
-+        if (IsFunctionCall)
-+          return;
-+      }
-+    }
- 
-     auto PCI = &CI;
-     if (DemangledName == kOCLBuiltinName::AtomicInit) {
-@@ -819,7 +872,7 @@ void OCL20ToSPIRV::transAtomicBuiltin(CallInst *CI, OCLBuiltinTransInfo &Info) {
-   AttributeList Attrs = CI->getCalledFunction()->getAttributes();
-   mutateCallInstSPIRV(
-       M, CI,
--      [=](CallInst *CI, std::vector<Value *> &Args) {
-+      [=](CallInst *CI, std::vector<Value *> &Args) -> std::string {
-         Info.PostProc(Args);
-         // Order of args in OCL20:
-         // object, 0-2 other args, 1-2 order, scope
-@@ -864,7 +917,21 @@ void OCL20ToSPIRV::transAtomicBuiltin(CallInst *CI, OCLBuiltinTransInfo &Info) {
-           std::rotate(Args.begin() + 2, Args.begin() + OrderIdx,
-                       Args.end() - Offset);
-         }
--        return getSPIRVFuncName(OCLSPIRVBuiltinMap::map(Info.UniqName));
-+	llvm::Type* AtomicBuiltinsReturnType =
-+            CI->getCalledFunction()->getReturnType();
-+        auto IsFPType = [](llvm::Type *ReturnType) {
-+          return ReturnType->isHalfTy() || ReturnType->isFloatTy() ||
-+                 ReturnType->isDoubleTy();
-+        };
-+        auto SPIRVFunctionName =
-+            getSPIRVFuncName(OCLSPIRVBuiltinMap::map(Info.UniqName));
-+        if (!IsFPType(AtomicBuiltinsReturnType))
-+          return SPIRVFunctionName;
-+        // Translate FP-typed atomic builtins.
-+        return llvm::StringSwitch<std::string>(SPIRVFunctionName)
-+            .Case("__spirv_AtomicIAdd", "__spirv_AtomicFAddEXT")
-+            .Case("__spirv_AtomicSMax", "__spirv_AtomicFMaxEXT")
-+            .Case("__spirv_AtomicSMin", "__spirv_AtomicFMinEXT");
-       },
-       &Attrs);
- }
-diff --git a/lib/SPIRV/SPIRVToOCL.h b/lib/SPIRV/SPIRVToOCL.h
-index ddeec0b6..006fb0b1 100644
---- a/lib/SPIRV/SPIRVToOCL.h
-+++ b/lib/SPIRV/SPIRVToOCL.h
-@@ -178,6 +178,9 @@ public:
-   /// using separate maps for OpenCL 1.2 and OpenCL 2.0
-   virtual Instruction *mutateAtomicName(CallInst *CI, Op OC) = 0;
- 
-+  // Transform FP atomic opcode to corresponding OpenCL function name
-+  virtual std::string mapFPAtomicName(Op OC) = 0;
-+
- private:
-   /// Transform uniform group opcode to corresponding OpenCL function name,
-   /// example: GroupIAdd(Reduce) => group_iadd => work_group_reduce_add |
-diff --git a/lib/SPIRV/SPIRVToOCL12.cpp b/lib/SPIRV/SPIRVToOCL12.cpp
-index afddd596..d7f00de3 100644
---- a/lib/SPIRV/SPIRVToOCL12.cpp
-+++ b/lib/SPIRV/SPIRVToOCL12.cpp
-@@ -104,6 +104,9 @@ public:
-   /// cl_khr_int64_base_atomics and cl_khr_int64_extended_atomics extensions.
-   std::string mapAtomicName(Op OC, Type *Ty);
- 
-+  // Transform FP atomic opcode to corresponding OpenCL function name
-+  std::string mapFPAtomicName(Op OC) override;
-+
-   static char ID;
- };
- 
-@@ -338,6 +341,21 @@ Instruction *SPIRVToOCL12::visitCallSPIRVAtomicBuiltin(CallInst *CI, Op OC) {
-   return NewCI;
- }
- 
-+std::string SPIRVToOCL12::mapFPAtomicName(Op OC) {
-+  assert(isFPAtomicOpCode(OC) && "Not intended to handle other opcodes than "
-+                                 "AtomicF{Add/Min/Max}EXT!");
-+  switch (OC) {
-+  case OpAtomicFAddEXT:
-+    return "atomic_add";
-+  case OpAtomicFMinEXT:
-+    return "atomic_min";
-+  case OpAtomicFMaxEXT:
-+    return "atomic_max";
-+  default:
-+    llvm_unreachable("Unsupported opcode!");
-+  }
-+}
-+
- Instruction *SPIRVToOCL12::mutateAtomicName(CallInst *CI, Op OC) {
-   AttributeList Attrs = CI->getCalledFunction()->getAttributes();
-   return mutateCallInstOCL(
-@@ -351,6 +369,9 @@ Instruction *SPIRVToOCL12::mutateAtomicName(CallInst *CI, Op OC) {
- std::string SPIRVToOCL12::mapAtomicName(Op OC, Type *Ty) {
-   std::string Prefix = Ty->isIntegerTy(64) ? kOCLBuiltinName::AtomPrefix
-                                            : kOCLBuiltinName::AtomicPrefix;
-+  // Map fp atomic instructions to regular OpenCL built-ins.
-+  if (isFPAtomicOpCode(OC))
-+    return mapFPAtomicName(OC);
-   return Prefix += OCL12SPIRVBuiltinMap::rmap(OC);
- }
- 
-diff --git a/lib/SPIRV/SPIRVToOCL20.cpp b/lib/SPIRV/SPIRVToOCL20.cpp
-index d829ff42..01d088e9 100644
---- a/lib/SPIRV/SPIRVToOCL20.cpp
-+++ b/lib/SPIRV/SPIRVToOCL20.cpp
-@@ -82,6 +82,9 @@ public:
-   /// compare_exchange_strong/weak_explicit
-   Instruction *visitCallSPIRVAtomicCmpExchg(CallInst *CI, Op OC) override;
- 
-+  // Transform FP atomic opcode to corresponding OpenCL function name
-+  std::string mapFPAtomicName(Op OC) override;
-+
-   static char ID;
- };
- 
-@@ -144,11 +147,29 @@ void SPIRVToOCL20::visitCallSPIRVControlBarrier(CallInst *CI) {
-       &Attrs);
- }
- 
-+std::string SPIRVToOCL20::mapFPAtomicName(Op OC) {
-+  assert(isFPAtomicOpCode(OC) && "Not intended to handle other opcodes than "
-+                                 "AtomicF{Add/Min/Max}EXT!");
-+  switch (OC) {
-+  case OpAtomicFAddEXT:
-+    return "atomic_fetch_add_explicit";
-+  case OpAtomicFMinEXT:
-+    return "atomic_fetch_min_explicit";
-+  case OpAtomicFMaxEXT:
-+    return "atomic_fetch_max_explicit";
-+  default:
-+    llvm_unreachable("Unsupported opcode!");
-+  }
-+}
-+
- Instruction *SPIRVToOCL20::mutateAtomicName(CallInst *CI, Op OC) {
-   AttributeList Attrs = CI->getCalledFunction()->getAttributes();
-   return mutateCallInstOCL(
-       M, CI,
-       [=](CallInst *, std::vector<Value *> &Args) {
-+        // Map fp atomic instructions to regular OpenCL built-ins.
-+        if (isFPAtomicOpCode(OC))
-+          return mapFPAtomicName(OC);
-         return OCLSPIRVBuiltinMap::rmap(OC);
-       },
-       &Attrs);
-@@ -215,7 +236,12 @@ CallInst *SPIRVToOCL20::mutateCommonAtomicArguments(CallInst *CI, Op OC) {
-           }
-         }
-         auto Ptr = findFirstPtr(Args);
--        auto Name = OCLSPIRVBuiltinMap::rmap(OC);
-+	std::string Name;
-+	// Map fp atomic instructions to regular OpenCL built-ins.
-+        if (isFPAtomicOpCode(OC))
-+          Name = mapFPAtomicName(OC);
-+        else
-+          Name = OCLSPIRVBuiltinMap::rmap(OC);
-         auto NumOrder = getSPIRVAtomicBuiltinNumMemoryOrderArgs(OC);
-         auto ScopeIdx = Ptr + 1;
-         auto OrderIdx = Ptr + 2;
-diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
-index 13f93fbe..7b707993 100644
---- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
-+++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
-@@ -521,7 +521,6 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
-   add(CapabilityAtomicFloat64AddEXT, "AtomicFloat64AddEXT");
-   add(CapabilityAtomicFloat32MinMaxEXT, "AtomicFloat32MinMaxEXT");
-   add(CapabilityAtomicFloat64MinMaxEXT, "AtomicFloat64MinMaxEXT");
--  add(CapabilityAtomicFloat16MinMaxEXT, "AtomicFloat16MinMaxEXT");
-   add(CapabilitySubgroupShuffleINTEL, "SubgroupShuffleINTEL");
-   add(CapabilitySubgroupBufferBlockIOINTEL, "SubgroupBufferBlockIOINTEL");
-   add(CapabilitySubgroupImageBlockIOINTEL, "SubgroupImageBlockIOINTEL");
-diff --git a/lib/SPIRV/libSPIRV/SPIRVOpCode.h b/lib/SPIRV/libSPIRV/SPIRVOpCode.h
-index feec70f6..8e595e83 100644
---- a/lib/SPIRV/libSPIRV/SPIRVOpCode.h
-+++ b/lib/SPIRV/libSPIRV/SPIRVOpCode.h
-@@ -54,11 +54,17 @@ template <> inline void SPIRVMap<Op, std::string>::init() {
- }
- SPIRV_DEF_NAMEMAP(Op, OpCodeNameMap)
- 
-+inline bool isFPAtomicOpCode(Op OpCode) {
-+  return OpCode == OpAtomicFAddEXT || OpCode == OpAtomicFMinEXT ||
-+         OpCode == OpAtomicFMaxEXT;
-+}
-+
- inline bool isAtomicOpCode(Op OpCode) {
-   static_assert(OpAtomicLoad < OpAtomicXor, "");
-   return ((unsigned)OpCode >= OpAtomicLoad &&
-           (unsigned)OpCode <= OpAtomicXor) ||
--         OpCode == OpAtomicFlagTestAndSet || OpCode == OpAtomicFlagClear;
-+         OpCode == OpAtomicFlagTestAndSet || OpCode == OpAtomicFlagClear ||
-+	 isFPAtomicOpCode(OpCode);
- }
- inline bool isBinaryOpCode(Op OpCode) {
-   return ((unsigned)OpCode >= OpIAdd && (unsigned)OpCode <= OpFMod) ||
-diff --git a/test/AtomicFAddEXTForOCL.ll b/test/AtomicFAddEXTForOCL.ll
-new file mode 100644
-index 00000000..fb146fb9
---- /dev/null
-+++ b/test/AtomicFAddEXTForOCL.ll
-@@ -0,0 +1,64 @@
-+; RUN: llvm-as %s -o %t.bc
-+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add -o %t.spv
-+; RUN: spirv-val %t.spv
-+; RUN: llvm-spirv -to-text %t.spv -o %t.spt
-+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
-+
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
-+
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
-+
-+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
-+target triple = "spir-unknown-unknown"
-+
-+; CHECK-SPIRV: Capability AtomicFloat32AddEXT
-+; CHECK-SPIRV: Capability AtomicFloat64AddEXT
-+; CHECK-SPIRV: Extension "SPV_EXT_shader_atomic_float_add"
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
-+
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_atomic_float(float addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_32]]
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_add_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call = tail call spir_func float @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)* %a, float 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func float @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)*, float, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_atomic_double(double addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_64]]
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_add_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+diid]]({{.*}})
-+  %call = tail call spir_func double @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)* %a, double 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+; Function Attrs: convergent
-+declare spir_func double @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)*, double, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #1 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #2 = { convergent nounwind }
-+
-+!llvm.module.flags = !{!0}
-+!opencl.ocl.version = !{!1}
-+!opencl.spir.version = !{!1}
-+!llvm.ident = !{!2}
-+
-+!0 = !{i32 1, !"wchar_size", i32 4}
-+!1 = !{i32 2, i32 0}
-+!2 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git 94aa388f0ce0723bb15503cf41c2c15b288375b9)"}
-diff --git a/test/AtomicFAddExt.ll b/test/AtomicFAddExt.ll
-index 011dd8a7..42bdfeea 100644
---- a/test/AtomicFAddExt.ll
-+++ b/test/AtomicFAddExt.ll
-@@ -4,20 +4,16 @@
- ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
- 
- ; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
--; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL12
- 
--target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
--target triple = "spir64-unknown-unknown-sycldevice"
--
--%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
--%"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" = type { [1 x i64] }
--%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
--
--$_ZTSZZ3addIfEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37 = comdat any
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
- 
--$_ZTSZZ3addIdEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37 = comdat any
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
- 
--@__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32
-+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
-+target triple = "spir64-unknown-unknown-sycldevice"
- 
- ; CHECK-SPIRV: Capability AtomicFloat32AddEXT
- ; CHECK-SPIRV: Capability AtomicFloat64AddEXT
-@@ -25,62 +21,43 @@ $_ZTSZZ3addIdEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_3
- ; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
- ; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
- 
--; Function Attrs: convergent norecurse mustprogress
--define weak_odr dso_local spir_kernel void @_ZTSZZ3addIfEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37(float addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, float addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func float @_Z14AtomicFloatIncRf(float addrspace(4)* align 4 dereferenceable(4) %Arg) local_unnamed_addr #0 {
- entry:
--  %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0
--  %1 = load i64, i64* %0, align 8
--  %add.ptr.i29 = getelementptr inbounds float, float addrspace(1)* %_arg_, i64 %1
--  %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0
--  %3 = load i64, i64* %2, align 8
--  %add.ptr.i = getelementptr inbounds float, float addrspace(1)* %_arg_4, i64 %3
--  %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !5
--  %5 = extractelement <3 x i64> %4, i64 0
-+  %0 = addrspacecast float addrspace(4)* %Arg to float addrspace(1)*
-   ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_32]]
--  ; CHECK-LLVM: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+]]({{.*}})
--  %call3.i.i.i.i = tail call spir_func float @_Z21__spirv_AtomicFAddEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)* %add.ptr.i29, i32 1, i32 896, float 1.000000e+00) #2
--  %add.i.i = fadd float %call3.i.i.i.i, 1.000000e+00
--  %sext.i = shl i64 %5, 32
--  %conv5.i = ashr exact i64 %sext.i, 32
--  %ptridx.i.i = getelementptr inbounds float, float addrspace(1)* %add.ptr.i, i64 %conv5.i
--  %ptridx.ascast.i.i = addrspacecast float addrspace(1)* %ptridx.i.i to float addrspace(4)*
--  store float %add.i.i, float addrspace(4)* %ptridx.ascast.i.i, align 4, !tbaa !14
--  ret void
-+  ; CHECK-LLVM-CL12: call spir_func float @[[FLOAT_FUNC_NAME:_Z10atomic_add[[:alnum:]]+ff]]({{.*}})
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_add_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call3.i.i = tail call spir_func float @_Z21__spirv_AtomicFAddEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)* %0, i32 1, i32 896, float 1.000000e+00) #2
-+  ret float %call3.i.i
- }
- 
- ; Function Attrs: convergent
--; CHECK-LLVM: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float addrspace(1)*, i32, i32, float)
- declare dso_local spir_func float @_Z21__spirv_AtomicFAddEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)*, i32, i32, float) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
- 
--; Function Attrs: convergent norecurse mustprogress
--define weak_odr dso_local spir_kernel void @_ZTSZZ3addIdEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37(double addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, double addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func double @_Z15AtomicDoubleIncRd(double addrspace(4)* align 8 dereferenceable(8) %Arg) local_unnamed_addr #0 {
- entry:
--  %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0
--  %1 = load i64, i64* %0, align 8
--  %add.ptr.i29 = getelementptr inbounds double, double addrspace(1)* %_arg_, i64 %1
--  %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0
--  %3 = load i64, i64* %2, align 8
--  %add.ptr.i = getelementptr inbounds double, double addrspace(1)* %_arg_4, i64 %3
--  %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !18
--  %5 = extractelement <3 x i64> %4, i64 0
-+  %0 = addrspacecast double addrspace(4)* %Arg to double addrspace(1)*
-   ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_64]]
--  ; CHECK-LLVM: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+]]({{.*}})
--  %call3.i.i.i.i = tail call spir_func double @_Z21__spirv_AtomicFAddEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)* %add.ptr.i29, i32 1, i32 896, double 1.000000e+00) #2
--  %add.i.i = fadd double %call3.i.i.i.i, 1.000000e+00
--  %sext.i = shl i64 %5, 32
--  %conv5.i = ashr exact i64 %sext.i, 32
--  %ptridx.i.i = getelementptr inbounds double, double addrspace(1)* %add.ptr.i, i64 %conv5.i
--  %ptridx.ascast.i.i = addrspacecast double addrspace(1)* %ptridx.i.i to double addrspace(4)*
--  store double %add.i.i, double addrspace(4)* %ptridx.ascast.i.i, align 8, !tbaa !27
--  ret void
-+  ; CHECK-LLVM-CL12: call spir_func double @[[DOUBLE_FUNC_NAME:_Z10atomic_add[[:alnum:]]+dd]]({{.*}})
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_add_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+diid]]({{.*}})
-+  %call3.i.i = tail call spir_func double @_Z21__spirv_AtomicFAddEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)* %0, i32 1, i32 896, double 1.000000e+00) #2
-+  ret double %call3.i.i
- }
- 
- ; Function Attrs: convergent
--; CHECK-LLVM: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double addrspace(1)*, i32, i32, double)
- declare dso_local spir_func double @_Z21__spirv_AtomicFAddEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)*, i32, i32, double) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
- 
--attributes #0 = { convergent norecurse }
--attributes #1 = { convergent }
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-+attributes #1 = { convergent "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
- attributes #2 = { convergent nounwind }
- 
- !llvm.module.flags = !{!0}
-@@ -91,29 +68,5 @@ attributes #2 = { convergent nounwind }
- !0 = !{i32 1, !"wchar_size", i32 4}
- !1 = !{i32 1, i32 2}
- !2 = !{i32 4, i32 100000}
--!3 = !{!"clang version 12.0.0"}
--!4 = !{i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1}
--!5 = !{!6, !8, !10, !12}
--!6 = distinct !{!6, !7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"}
--!7 = distinct !{!7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"}
--!8 = distinct !{!8, !9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"}
--!9 = distinct !{!9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"}
--!10 = distinct !{!10, !11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"}
--!11 = distinct !{!11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"}
--!12 = distinct !{!12, !13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"}
--!13 = distinct !{!13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"}
--!14 = !{!15, !15, i64 0}
--!15 = !{!"float", !16, i64 0}
--!16 = !{!"omnipotent char", !17, i64 0}
--!17 = !{!"Simple C++ TBAA"}
--!18 = !{!19, !21, !23, !25}
--!19 = distinct !{!19, !20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"}
--!20 = distinct !{!20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"}
--!21 = distinct !{!21, !22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"}
--!22 = distinct !{!22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"}
--!23 = distinct !{!23, !24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"}
--!24 = distinct !{!24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"}
--!25 = distinct !{!25, !26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"}
--!26 = distinct !{!26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"}
--!27 = !{!28, !28, i64 0}
--!28 = !{!"double", !16, i64 0}
-+!3 = !{!"clang version 13.0.0"}
-+
-diff --git a/test/AtomicFMaxEXT.ll b/test/AtomicFMaxEXT.ll
-index 1b81e53b..1c2eec93 100644
---- a/test/AtomicFMaxEXT.ll
-+++ b/test/AtomicFMaxEXT.ll
-@@ -4,20 +4,16 @@
- ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
- 
- ; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
--; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL12
- 
--target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
--target triple = "spir64-unknown-unknown-sycldevice"
--
--%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
--%"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" = type { [1 x i64] }
--%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
--
--$_ZTSZZ8max_testIfEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37 = comdat any
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
- 
--$_ZTSZZ8max_testIdEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37 = comdat any
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
- 
--@__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32
-+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
-+target triple = "spir64-unknown-unknown-sycldevice"
- 
- ; CHECK-SPIRV: Capability AtomicFloat32MinMaxEXT
- ; CHECK-SPIRV: Capability AtomicFloat64MinMaxEXT
-@@ -25,65 +21,42 @@ $_ZTSZZ8max_testIdEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4item
- ; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
- ; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
- 
--; Function Attrs: convergent norecurse
--define weak_odr dso_local spir_kernel void @_ZTSZZ8max_testIfEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37(float addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, float addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func float @_Z14AtomicFloatMaxRf(float addrspace(4)* align 4 dereferenceable(4) %Arg) local_unnamed_addr #0 {
- entry:
--  %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0
--  %1 = load i64, i64* %0, align 8
--  %add.ptr.i29 = getelementptr inbounds float, float addrspace(1)* %_arg_, i64 %1
--  %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0
--  %3 = load i64, i64* %2, align 8
--  %add.ptr.i = getelementptr inbounds float, float addrspace(1)* %_arg_4, i64 %3
--  %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !5
--  %5 = extractelement <3 x i64> %4, i64 0
--  %conv.i = trunc i64 %5 to i32
--  %conv3.i = sitofp i32 %conv.i to float
--  %add.i = fadd float %conv3.i, 1.000000e+00
-+  %0 = addrspacecast float addrspace(4)* %Arg to float addrspace(1)*
-   ; CHECK-SPIRV: 7 AtomicFMaxEXT [[TYPE_FLOAT_32]]
--  ; CHECK-LLVM: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+]]({{.*}})
--  %call3.i.i.i = tail call spir_func float @_Z21__spirv_AtomicFMaxEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)* %add.ptr.i29, i32 1, i32 896, float %add.i) #2
--  %sext.i = shl i64 %5, 32
--  %conv6.i = ashr exact i64 %sext.i, 32
--  %ptridx.i.i = getelementptr inbounds float, float addrspace(1)* %add.ptr.i, i64 %conv6.i
--  %ptridx.ascast.i.i = addrspacecast float addrspace(1)* %ptridx.i.i to float addrspace(4)*
--  store float %call3.i.i.i, float addrspace(4)* %ptridx.ascast.i.i, align 4, !tbaa !14
--  ret void
-+  ; CHECK-LLVM-CL12: call spir_func float @[[FLOAT_FUNC_NAME:_Z10atomic_max[[:alnum:]]+ff]]({{.*}})
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_max_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call.i.i.i = tail call spir_func float @_Z21__spirv_AtomicFMaxEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)* %0, i32 1, i32 896, float 1.000000e+00) #2
-+  ret float %call.i.i.i
- }
- 
- ; Function Attrs: convergent
--; CHECK-LLVM: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float addrspace(1)*, i32, i32, float)
- declare dso_local spir_func float @_Z21__spirv_AtomicFMaxEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)*, i32, i32, float) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
- 
--; Function Attrs: convergent norecurse
--define weak_odr dso_local spir_kernel void @_ZTSZZ8max_testIdEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37(double addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, double addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func double @_Z15AtomicDoubleMaxRd(double addrspace(4)* align 8 dereferenceable(8) %Arg) local_unnamed_addr #0 {
- entry:
--  %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0
--  %1 = load i64, i64* %0, align 8
--  %add.ptr.i29 = getelementptr inbounds double, double addrspace(1)* %_arg_, i64 %1
--  %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0
--  %3 = load i64, i64* %2, align 8
--  %add.ptr.i = getelementptr inbounds double, double addrspace(1)* %_arg_4, i64 %3
--  %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !18
--  %5 = extractelement <3 x i64> %4, i64 0
--  %conv.i = trunc i64 %5 to i32
--  %conv3.i = sitofp i32 %conv.i to double
--  %add.i = fadd double %conv3.i, 1.000000e+00
-+  %0 = addrspacecast double addrspace(4)* %Arg to double addrspace(1)*
-   ; CHECK-SPIRV: 7 AtomicFMaxEXT [[TYPE_FLOAT_64]]
--  ; CHECK-LLVM: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+]]({{.*}})
--  %call3.i.i.i = tail call spir_func double @_Z21__spirv_AtomicFMaxEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)* %add.ptr.i29, i32 1, i32 896, double %add.i) #2
--  %sext.i = shl i64 %5, 32
--  %conv6.i = ashr exact i64 %sext.i, 32
--  %ptridx.i.i = getelementptr inbounds double, double addrspace(1)* %add.ptr.i, i64 %conv6.i
--  %ptridx.ascast.i.i = addrspacecast double addrspace(1)* %ptridx.i.i to double addrspace(4)*
--  store double %call3.i.i.i, double addrspace(4)* %ptridx.ascast.i.i, align 8, !tbaa !27
--  ret void
-+  ; CHECK-LLVM-CL12: call spir_func double @[[DOUBLE_FUNC_NAME:_Z10atomic_max[[:alnum:]]+dd]]({{.*}})
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_max_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+diid]]({{.*}})
-+  %call.i.i.i = tail call spir_func double @_Z21__spirv_AtomicFMaxEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)* %0, i32 1, i32 896, double 1.000000e+00) #2
-+  ret double %call.i.i.i
- }
- 
- ; Function Attrs: convergent
--; CHECK-LLVM: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double addrspace(1)*, i32, i32, double)
- declare dso_local spir_func double @_Z21__spirv_AtomicFMaxEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)*, i32, i32, double) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
- 
--attributes #0 = { convergent norecurse "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
- attributes #1 = { convergent "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
- attributes #2 = { convergent nounwind }
- 
-@@ -95,29 +68,5 @@ attributes #2 = { convergent nounwind }
- !0 = !{i32 1, !"wchar_size", i32 4}
- !1 = !{i32 1, i32 2}
- !2 = !{i32 4, i32 100000}
--!3 = !{!"clang version 12.0.0"}
--!4 = !{i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1}
--!5 = !{!6, !8, !10, !12}
--!6 = distinct !{!6, !7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"}
--!7 = distinct !{!7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"}
--!8 = distinct !{!8, !9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"}
--!9 = distinct !{!9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"}
--!10 = distinct !{!10, !11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"}
--!11 = distinct !{!11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"}
--!12 = distinct !{!12, !13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"}
--!13 = distinct !{!13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"}
--!14 = !{!15, !15, i64 0}
--!15 = !{!"float", !16, i64 0}
--!16 = !{!"omnipotent char", !17, i64 0}
--!17 = !{!"Simple C++ TBAA"}
--!18 = !{!19, !21, !23, !25}
--!19 = distinct !{!19, !20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"}
--!20 = distinct !{!20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"}
--!21 = distinct !{!21, !22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"}
--!22 = distinct !{!22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"}
--!23 = distinct !{!23, !24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"}
--!24 = distinct !{!24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"}
--!25 = distinct !{!25, !26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"}
--!26 = distinct !{!26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"}
--!27 = !{!28, !28, i64 0}
--!28 = !{!"double", !16, i64 0}
-+!3 = !{!"clang version 13.0.0"}
-+
-diff --git a/test/AtomicFMaxEXTForOCL.ll b/test/AtomicFMaxEXTForOCL.ll
-new file mode 100644
-index 00000000..1f2530d9
---- /dev/null
-+++ b/test/AtomicFMaxEXTForOCL.ll
-@@ -0,0 +1,64 @@
-+; RUN: llvm-as %s -o %t.bc
-+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_EXT_shader_atomic_float_min_max -o %t.spv
-+; RUN: spirv-val %t.spv
-+; RUN: llvm-spirv -to-text %t.spv -o %t.spt
-+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
-+
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
-+
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
-+
-+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
-+target triple = "spir-unknown-unknown"
-+
-+; CHECK-SPIRV: Capability AtomicFloat32MinMaxEXT
-+; CHECK-SPIRV: Capability AtomicFloat64MinMaxEXT
-+; CHECK-SPIRV: Extension "SPV_EXT_shader_atomic_float_min_max"
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_float(float addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMaxEXT [[TYPE_FLOAT_32]]
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_max_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call = tail call spir_func float @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)* %a, float 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func float @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)*, float, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_double(double addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMaxEXT [[TYPE_FLOAT_64]]
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_max_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+diid]]({{.*}})
-+  %call = tail call spir_func double @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)* %a, double 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func double @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)*, double, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #1 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #2 = { convergent nounwind }
-+
-+!llvm.module.flags = !{!0}
-+!opencl.ocl.version = !{!1}
-+!opencl.spir.version = !{!1}
-+!llvm.ident = !{!2}
-+
-+!0 = !{i32 1, !"wchar_size", i32 4}
-+!1 = !{i32 2, i32 0}
-+!2 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git 94aa388f0ce0723bb15503cf41c2c15b288375b9)"}
-diff --git a/test/AtomicFMinEXT.ll b/test/AtomicFMinEXT.ll
-index 98c98b8e..9e40a669 100644
---- a/test/AtomicFMinEXT.ll
-+++ b/test/AtomicFMinEXT.ll
-@@ -4,20 +4,16 @@
- ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
- 
- ; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
--; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL12
- 
--target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
--target triple = "spir64-unknown-unknown-sycldevice"
--
--%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
--%"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" = type { [1 x i64] }
--%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
--
--$_ZTSZZ8min_testIfEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37 = comdat any
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
- 
--$_ZTSZZ8min_testIdEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37 = comdat any
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
- 
--@__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32
-+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
-+target triple = "spir64-unknown-unknown-sycldevice"
- 
- ; CHECK-SPIRV: Capability AtomicFloat32MinMaxEXT
- ; CHECK-SPIRV: Capability AtomicFloat64MinMaxEXT
-@@ -25,65 +21,42 @@ $_ZTSZZ8min_testIdEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4item
- ; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
- ; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
- 
--; Function Attrs: convergent norecurse
--define weak_odr dso_local spir_kernel void @_ZTSZZ8min_testIfEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37(float addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, float addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func float @_Z14AtomicFloatMinRf(float addrspace(4)* align 4 dereferenceable(4) %Arg) local_unnamed_addr #0 {
- entry:
--  %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0
--  %1 = load i64, i64* %0, align 8
--  %add.ptr.i29 = getelementptr inbounds float, float addrspace(1)* %_arg_, i64 %1
--  %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0
--  %3 = load i64, i64* %2, align 8
--  %add.ptr.i = getelementptr inbounds float, float addrspace(1)* %_arg_4, i64 %3
--  %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !5
--  %5 = extractelement <3 x i64> %4, i64 0
--  %conv.i = trunc i64 %5 to i32
--  %conv3.i = sitofp i32 %conv.i to float
--  %add.i = fadd float %conv3.i, 1.000000e+00
-+  %0 = addrspacecast float addrspace(4)* %Arg to float addrspace(1)*
-   ; CHECK-SPIRV: 7 AtomicFMinEXT [[TYPE_FLOAT_32]]
--  ; CHECK-LLVM: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+]]({{.*}})
--  %call3.i.i.i = tail call spir_func float @_Z21__spirv_AtomicFMinEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)* %add.ptr.i29, i32 1, i32 896, float %add.i) #2
--  %sext.i = shl i64 %5, 32
--  %conv6.i = ashr exact i64 %sext.i, 32
--  %ptridx.i.i = getelementptr inbounds float, float addrspace(1)* %add.ptr.i, i64 %conv6.i
--  %ptridx.ascast.i.i = addrspacecast float addrspace(1)* %ptridx.i.i to float addrspace(4)*
--  store float %call3.i.i.i, float addrspace(4)* %ptridx.ascast.i.i, align 4, !tbaa !14
--  ret void
-+  ; CHECK-LLVM-CL12: call spir_func float @[[FLOAT_FUNC_NAME:_Z10atomic_min[[:alnum:]]+ff]]({{.*}})
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_min_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call.i.i.i = tail call spir_func float @_Z21__spirv_AtomicFMinEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)* %0, i32 1, i32 896, float 1.000000e+00) #2
-+  ret float %call.i.i.i
- }
- 
- ; Function Attrs: convergent
--; CHECK-LLVM: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float addrspace(1)*, i32, i32, float)
- declare dso_local spir_func float @_Z21__spirv_AtomicFMinEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)*, i32, i32, float) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
- 
--; Function Attrs: convergent norecurse
--define weak_odr dso_local spir_kernel void @_ZTSZZ8min_testIdEvN2cl4sycl5queueEmENKUlRNS1_7handlerEE16_14clES4_EUlNS1_4itemILi1ELb1EEEE19_37(double addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, double addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 {
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func double @_Z15AtomicDoubleMinRd(double addrspace(4)* align 8 dereferenceable(8) %Arg) local_unnamed_addr #0 {
- entry:
--  %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0
--  %1 = load i64, i64* %0, align 8
--  %add.ptr.i29 = getelementptr inbounds double, double addrspace(1)* %_arg_, i64 %1
--  %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0
--  %3 = load i64, i64* %2, align 8
--  %add.ptr.i = getelementptr inbounds double, double addrspace(1)* %_arg_4, i64 %3
--  %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !18
--  %5 = extractelement <3 x i64> %4, i64 0
--  %conv.i = trunc i64 %5 to i32
--  %conv3.i = sitofp i32 %conv.i to double
--  %add.i = fadd double %conv3.i, 1.000000e+00
-+  %0 = addrspacecast double addrspace(4)* %Arg to double addrspace(1)*
-   ; CHECK-SPIRV: 7 AtomicFMinEXT [[TYPE_FLOAT_64]]
--  ; CHECK-LLVM: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+]]({{.*}})
--  %call3.i.i.i = tail call spir_func double @_Z21__spirv_AtomicFMinEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)* %add.ptr.i29, i32 1, i32 896, double %add.i) #2
--  %sext.i = shl i64 %5, 32
--  %conv6.i = ashr exact i64 %sext.i, 32
--  %ptridx.i.i = getelementptr inbounds double, double addrspace(1)* %add.ptr.i, i64 %conv6.i
--  %ptridx.ascast.i.i = addrspacecast double addrspace(1)* %ptridx.i.i to double addrspace(4)*
--  store double %call3.i.i.i, double addrspace(4)* %ptridx.ascast.i.i, align 8, !tbaa !27
--  ret void
-+  ; CHECK-LLVM-CL12: call spir_func double @[[DOUBLE_FUNC_NAME:_Z10atomic_min[[:alnum:]]+dd]]({{.*}})
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_min_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+diid]]({{.*}})
-+  %call.i.i.i = tail call spir_func double @_Z21__spirv_AtomicFMinEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)* %0, i32 1, i32 896, double 1.000000e+00) #2
-+  ret double %call.i.i.i
- }
- 
- ; Function Attrs: convergent
--; CHECK-LLVM: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double addrspace(1)*, i32, i32, double)
- declare dso_local spir_func double @_Z21__spirv_AtomicFMinEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)*, i32, i32, double) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
- 
--attributes #0 = { convergent norecurse "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
- attributes #1 = { convergent "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
- attributes #2 = { convergent nounwind }
- 
-@@ -95,29 +68,5 @@ attributes #2 = { convergent nounwind }
- !0 = !{i32 1, !"wchar_size", i32 4}
- !1 = !{i32 1, i32 2}
- !2 = !{i32 4, i32 100000}
--!3 = !{!"clang version 12.0.0 (https://github.com/otcshare/llvm.git 67add71766d55d6a8d8d894822f583d6365a3b7d)"}
--!4 = !{i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1}
--!5 = !{!6, !8, !10, !12}
--!6 = distinct !{!6, !7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"}
--!7 = distinct !{!7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"}
--!8 = distinct !{!8, !9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"}
--!9 = distinct !{!9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"}
--!10 = distinct !{!10, !11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"}
--!11 = distinct !{!11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"}
--!12 = distinct !{!12, !13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"}
--!13 = distinct !{!13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"}
--!14 = !{!15, !15, i64 0}
--!15 = !{!"float", !16, i64 0}
--!16 = !{!"omnipotent char", !17, i64 0}
--!17 = !{!"Simple C++ TBAA"}
--!18 = !{!19, !21, !23, !25}
--!19 = distinct !{!19, !20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"}
--!20 = distinct !{!20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"}
--!21 = distinct !{!21, !22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"}
--!22 = distinct !{!22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"}
--!23 = distinct !{!23, !24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"}
--!24 = distinct !{!24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"}
--!25 = distinct !{!25, !26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"}
--!26 = distinct !{!26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"}
--!27 = !{!28, !28, i64 0}
--!28 = !{!"double", !16, i64 0}
-+!3 = !{!"clang version 13.0.0"}
-+
-diff --git a/test/AtomicFMinEXTForOCL.ll b/test/AtomicFMinEXTForOCL.ll
-new file mode 100644
-index 00000000..6196b0f8
---- /dev/null
-+++ b/test/AtomicFMinEXTForOCL.ll
-@@ -0,0 +1,64 @@
-+; RUN: llvm-as %s -o %t.bc
-+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_EXT_shader_atomic_float_min_max -o %t.spv
-+; RUN: spirv-val %t.spv
-+; RUN: llvm-spirv -to-text %t.spv -o %t.spt
-+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
-+
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
-+
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
-+
-+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
-+target triple = "spir-unknown-unknown"
-+
-+; CHECK-SPIRV: Capability AtomicFloat32MinMaxEXT
-+; CHECK-SPIRV: Capability AtomicFloat64MinMaxEXT
-+; CHECK-SPIRV: Extension "SPV_EXT_shader_atomic_float_min_max"
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_float(float addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMinEXT [[TYPE_FLOAT_32]]
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_min_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call = tail call spir_func float @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)* %a, float 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func float @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)*, float, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_double(double addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMinEXT [[TYPE_FLOAT_64]]
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_min_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+diid]]({{.*}})
-+  %call = tail call spir_func double @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)* %a, double 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func double @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)*, double, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #1 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #2 = { convergent nounwind }
-+
-+!llvm.module.flags = !{!0}
-+!opencl.ocl.version = !{!1}
-+!opencl.spir.version = !{!1}
-+!llvm.ident = !{!2}
-+
-+!0 = !{i32 1, !"wchar_size", i32 4}
-+!1 = !{i32 2, i32 0}
-+!2 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git 94aa388f0ce0723bb15503cf41c2c15b288375b9)"}
-diff --git a/test/InvalidAtomicBuiltins.cl b/test/InvalidAtomicBuiltins.cl
-index b8ec5b89..2182f070 100644
---- a/test/InvalidAtomicBuiltins.cl
-+++ b/test/InvalidAtomicBuiltins.cl
-@@ -41,13 +41,9 @@ float __attribute__((overloadable)) atomic_fetch_xor(volatile generic atomic_flo
- double __attribute__((overloadable)) atomic_fetch_and(volatile generic atomic_double *object, double operand, memory_order order);
- double __attribute__((overloadable)) atomic_fetch_max(volatile generic atomic_double *object, double operand, memory_order order);
- double __attribute__((overloadable)) atomic_fetch_min(volatile generic atomic_double *object, double operand, memory_order order);
--float __attribute__((overloadable)) atomic_fetch_add_explicit(volatile generic atomic_float *object, float operand, memory_order order);
--float __attribute__((overloadable)) atomic_fetch_sub_explicit(volatile generic atomic_float *object, float operand, memory_order order);
- float __attribute__((overloadable)) atomic_fetch_or_explicit(volatile generic atomic_float *object, float operand, memory_order order);
- float __attribute__((overloadable)) atomic_fetch_xor_explicit(volatile generic atomic_float *object, float operand, memory_order order);
- double __attribute__((overloadable)) atomic_fetch_and_explicit(volatile generic atomic_double *object, double operand, memory_order order);
--double __attribute__((overloadable)) atomic_fetch_max_explicit(volatile generic atomic_double *object, double operand, memory_order order);
--double __attribute__((overloadable)) atomic_fetch_min_explicit(volatile generic atomic_double *object, double operand, memory_order order);
- 
- __kernel void test_atomic_fn(volatile __global float *p,
-                              volatile __global double *pp,
-@@ -86,11 +82,7 @@ __kernel void test_atomic_fn(volatile __global float *p,
-     d = atomic_fetch_and(pp, val, order);
-     d = atomic_fetch_min(pp, val, order);
-     d = atomic_fetch_max(pp, val, order);
--    f = atomic_fetch_add_explicit(p, val, order);
--    f = atomic_fetch_sub_explicit(p, val, order);
-     f = atomic_fetch_or_explicit(p, val, order);
-     f = atomic_fetch_xor_explicit(p, val, order);
-     d = atomic_fetch_and_explicit(pp, val, order);
--    d = atomic_fetch_min_explicit(pp, val, order);
--    d = atomic_fetch_max_explicit(pp, val, order);
- }
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0003-Memory-leak-fix-for-Managed-Static-Mutex.patch

@@ -1,35 +0,0 @@
-From cfb18b75e8a353bc7486f337541476a36994b063 Mon Sep 17 00:00:00 2001
-From: juanrod2 <>
-Date: Tue, 22 Dec 2020 08:33:08 +0800
-Subject: [PATCH 3/7] Memory leak fix for Managed Static Mutex
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-100/patches/llvm/0001-Memory-leak-fix-for-Managed-Static-Mutex.patch]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
-
-Cleaning a mutex inside ManagedStatic llvm class.
----
- llvm/lib/Support/ManagedStatic.cpp | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/llvm/lib/Support/ManagedStatic.cpp b/llvm/lib/Support/ManagedStatic.cpp
-index 053493f72fb5..6571580ccecf 100644
---- a/llvm/lib/Support/ManagedStatic.cpp
-+++ b/llvm/lib/Support/ManagedStatic.cpp
-@@ -76,8 +76,12 @@ void ManagedStaticBase::destroy() const {
- 
- /// llvm_shutdown - Deallocate and destroy all ManagedStatic variables.
- void llvm::llvm_shutdown() {
--  std::lock_guard<std::recursive_mutex> Lock(*getManagedStaticMutex());
-+  getManagedStaticMutex()->lock();
- 
-   while (StaticList)
-     StaticList->destroy();
-+
-+  getManagedStaticMutex()->unlock();
-+  delete ManagedStaticMutex;
-+  ManagedStaticMutex = nullptr;
- }
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0004-Remove-repo-name-in-LLVM-IR.patch

@@ -1,49 +0,0 @@
-From b794037bf1f90a93efa4c542855ad569cb13b4c5 Mon Sep 17 00:00:00 2001
-From: Feng Zou <feng.zou@intel.com>
-Date: Mon, 19 Oct 2020 14:43:38 +0800
-Subject: [PATCH 4/7] Remove repo name in LLVM IR
-
-Upstream-Status: Backport [Taken from opencl-clang patches, https://github.com/intel/opencl-clang/blob/ocl-open-100/patches/llvm/0003-Remove-repo-name-in-LLVM-IR.patch]
-Signed-off-by: Feng Zou <feng.zou@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/cmake/modules/VersionFromVCS.cmake | 23 ++++++++++++-----------
- 1 file changed, 12 insertions(+), 11 deletions(-)
-
-diff --git a/llvm/cmake/modules/VersionFromVCS.cmake b/llvm/cmake/modules/VersionFromVCS.cmake
-index 1b6519b4b7c4..8fd6b23bb345 100644
---- a/llvm/cmake/modules/VersionFromVCS.cmake
-+++ b/llvm/cmake/modules/VersionFromVCS.cmake
-@@ -33,17 +33,18 @@ function(get_source_info path revision repository)
-       else()
-         set(remote "origin")
-       endif()
--      execute_process(COMMAND ${GIT_EXECUTABLE} remote get-url ${remote}
--        WORKING_DIRECTORY ${path}
--        RESULT_VARIABLE git_result
--        OUTPUT_VARIABLE git_output
--        ERROR_QUIET)
--      if(git_result EQUAL 0)
--        string(STRIP "${git_output}" git_output)
--        set(${repository} ${git_output} PARENT_SCOPE)
--      else()
--        set(${repository} ${path} PARENT_SCOPE)
--      endif()
-+      # Do not show repo name in IR
-+      # execute_process(COMMAND ${GIT_EXECUTABLE} remote get-url ${remote}
-+      #   WORKING_DIRECTORY ${path}
-+      #   RESULT_VARIABLE git_result
-+      #   OUTPUT_VARIABLE git_output
-+      #   ERROR_QUIET)
-+      # if(git_result EQUAL 0)
-+      #   string(STRIP "${git_output}" git_output)
-+      #   set(${repository} ${git_output} PARENT_SCOPE)
-+      # else()
-+      #   set(${repository} ${path} PARENT_SCOPE)
-+      # endif()
-     endif()
-   endif()
- endfunction()
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0005-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch

@@ -1,47 +0,0 @@
-From 3dd4766499d25e5978a5d90001f18e657e875da0 Mon Sep 17 00:00:00 2001
-From: haonanya <haonan.yang@intel.com>
-Date: Thu, 12 Aug 2021 15:48:34 +0800
-Subject: [PATCH 5/7] Remove __IMAGE_SUPPORT__ macro for SPIR since SPIR
- doesn't require image support
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-100/patches/clang/0003-Remove-__IMAGE_SUPPORT__-macro-for-SPIR.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/Frontend/InitPreprocessor.cpp     | 3 ---
- clang/test/Preprocessor/predefined-macros.c | 4 ----
- 2 files changed, 7 deletions(-)
-
-diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp
-index aefd208e6cd3..b4a84636673a 100644
---- a/clang/lib/Frontend/InitPreprocessor.cpp
-+++ b/clang/lib/Frontend/InitPreprocessor.cpp
-@@ -1108,9 +1108,6 @@ static void InitializePredefinedMacros(const TargetInfo &TI,
-   if (TI.getSupportedOpenCLOpts().isSupported(#Ext))                           \
-     Builder.defineMacro(#Ext);
- #include "clang/Basic/OpenCLExtensions.def"
--
--    if (TI.getTriple().isSPIR())
--      Builder.defineMacro("__IMAGE_SUPPORT__");
-   }
- 
-   if (TI.hasInt128Type() && LangOpts.CPlusPlus && LangOpts.GNUMode) {
-diff --git a/clang/test/Preprocessor/predefined-macros.c b/clang/test/Preprocessor/predefined-macros.c
-index b088a37ba665..39a222d02faf 100644
---- a/clang/test/Preprocessor/predefined-macros.c
-+++ b/clang/test/Preprocessor/predefined-macros.c
-@@ -184,10 +184,6 @@
- // MSCOPE:#define __OPENCL_MEMORY_SCOPE_WORK_GROUP 1
- // MSCOPE:#define __OPENCL_MEMORY_SCOPE_WORK_ITEM 0
- 
--// RUN: %clang_cc1 %s -E -dM -o - -x cl -triple spir-unknown-unknown \
--// RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SPIR
--// CHECK-SPIR: #define __IMAGE_SUPPORT__ 1
--
- // RUN: %clang_cc1 %s -E -dM -o - -x hip -triple amdgcn-amd-amdhsa \
- // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-HIP
- // CHECK-HIP-NOT: #define __CUDA_ARCH__
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0006-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch

@@ -1,53 +0,0 @@
-From 2c53abd0008bbecfcfe871c6060f4bbf1c94c74a Mon Sep 17 00:00:00 2001
-From: Raphael Isemann <teemperor@gmail.com>
-Date: Thu, 1 Apr 2021 18:41:44 +0200
-Subject: [PATCH 6/7] Avoid calling ParseCommandLineOptions in BackendUtil if
- possible
-
-Calling `ParseCommandLineOptions` should only be called from `main` as the
-CommandLine setup code isn't thread-safe. As BackendUtil is part of the
-generic Clang FrontendAction logic, a process which has several threads executing
-Clang FrontendActions will randomly crash in the unsafe setup code.
-
-This patch avoids calling the function unless either the debug-pass option or
-limit-float-precision option is set. Without these two options set the
-`ParseCommandLineOptions` call doesn't do anything beside parsing
-the command line `clang` which doesn't set any options.
-
-See also D99652 where LLDB received a workaround for this crash.
-
-Reviewed By: JDevlieghere
-
-Differential Revision: https://reviews.llvm.org/D99740
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-100/patches/clang/0004-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch]
-
-Signed-off-by: Raphael Isemann <teemperor@gmail.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/CodeGen/BackendUtil.cpp | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
-index 0bfcab88a3a9..db8fd4166d7a 100644
---- a/clang/lib/CodeGen/BackendUtil.cpp
-+++ b/clang/lib/CodeGen/BackendUtil.cpp
-@@ -743,7 +743,15 @@ static void setCommandLineOpts(const CodeGenOptions &CodeGenOpts) {
-     BackendArgs.push_back("-limit-float-precision");
-     BackendArgs.push_back(CodeGenOpts.LimitFloatPrecision.c_str());
-   }
-+  // Check for the default "clang" invocation that won't set any cl::opt values.
-+  // Skip trying to parse the command line invocation to avoid the issues
-+  // described below.
-+  if (BackendArgs.size() == 1)
-+    return;
-   BackendArgs.push_back(nullptr);
-+  // FIXME: The command line parser below is not thread-safe and shares a global
-+  // state, so this call might crash or overwrite the options of another Clang
-+  // instance in the same process.
-   llvm::cl::ParseCommandLineOptions(BackendArgs.size() - 1,
-                                     BackendArgs.data());
- }
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0007-support-cl_ext_float_atomics.patch

@@ -1,377 +0,0 @@
-From a685de6fc45afcdbe4a7120e9d5b33e175dd71cd Mon Sep 17 00:00:00 2001
-From: haonanya <haonan.yang@intel.com>
-Date: Fri, 13 Aug 2021 10:00:02 +0800
-Subject: [PATCH 7/7] support cl_ext_float_atomics
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-100/patches/clang/0005-OpenCL-support-cl_ext_float_atomics.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/Headers/opencl-c-base.h     |  25 ++++
- clang/lib/Headers/opencl-c.h          | 208 ++++++++++++++++++++++++++
- clang/test/Headers/opencl-c-header.cl |  96 ++++++++++++
- 3 files changed, 329 insertions(+)
-
-diff --git a/clang/lib/Headers/opencl-c-base.h b/clang/lib/Headers/opencl-c-base.h
-index 2cc688ccc3da..86bbee12fdf8 100644
---- a/clang/lib/Headers/opencl-c-base.h
-+++ b/clang/lib/Headers/opencl-c-base.h
-@@ -14,6 +14,31 @@
-   #define CL_VERSION_3_0 300
- #endif
- 
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+// For SPIR all extensions are supported.
-+#if defined(__SPIR__)
-+#define cl_ext_float_atomics 1
-+#ifdef cl_khr_fp16
-+#define __opencl_c_ext_fp16_global_atomic_load_store 1
-+#define __opencl_c_ext_fp16_local_atomic_load_store 1
-+#define __opencl_c_ext_fp16_global_atomic_add 1
-+#define __opencl_c_ext_fp16_local_atomic_add 1
-+#define __opencl_c_ext_fp16_global_atomic_min_max 1
-+#define __opencl_c_ext_fp16_local_atomic_min_max 1
-+#endif
-+#ifdef __opencl_c_fp64
-+#define __opencl_c_ext_fp64_global_atomic_add 1
-+#define __opencl_c_ext_fp64_local_atomic_add 1
-+#define __opencl_c_ext_fp64_global_atomic_min_max 1
-+#define __opencl_c_ext_fp64_local_atomic_min_max 1
-+#endif
-+#define __opencl_c_ext_fp32_global_atomic_add 1
-+#define __opencl_c_ext_fp32_local_atomic_add 1
-+#define __opencl_c_ext_fp32_global_atomic_min_max 1
-+#define __opencl_c_ext_fp32_local_atomic_min_max 1
-+#endif // defined(__SPIR__)
-+#endif // (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+
- // Define features for 2.0 for header backward compatibility
- #ifndef __opencl_c_int64
-   #define __opencl_c_int64 1
-diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h
-index 67d900eb1c3d..b463e702d95e 100644
---- a/clang/lib/Headers/opencl-c.h
-+++ b/clang/lib/Headers/opencl-c.h
-@@ -14354,6 +14354,214 @@ intptr_t __ovld atomic_fetch_max_explicit(
-        // defined(cl_khr_int64_extended_atomics)
- #endif // (__OPENCL_C_VERSION__ >= CL_VERSION_3_0)
- 
-+#if defined(cl_ext_float_atomics)
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_max(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_min_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp32_global_atomic_min_max)
-+
-+#if defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_max(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_min_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_max(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_min_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp32_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+
-+#if defined(__opencl_c_ext_fp64_global_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_max(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_min_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp64_global_atomic_min_max)
-+
-+#if defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_max(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_min_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+
-+#if defined(__opencl_c_ext_fp64_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_max(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_min_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp64_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_add)
-+float __ovld atomic_fetch_add(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_sub(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_add_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp32_global_atomic_add)
-+
-+#if defined(__opencl_c_ext_fp32_local_atomic_add)
-+float __ovld atomic_fetch_add(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_sub(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_add_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp32_local_atomic_add)
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp32_local_atomic_add)
-+float __ovld atomic_fetch_add(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_sub(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_add_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp32_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp32_local_atomic_add)
-+
-+#if defined(__opencl_c_ext_fp64_global_atomic_add)
-+double __ovld atomic_fetch_add(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_sub(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_add_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp64_global_atomic_add)
-+
-+#if defined(__opencl_c_ext_fp64_local_atomic_add)
-+double __ovld atomic_fetch_add(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_sub(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_add_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp64_local_atomic_add)
-+
-+#if defined(__opencl_c_ext_fp64_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp64_local_atomic_add)
-+double __ovld atomic_fetch_add(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_sub(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_add_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif // defined(__opencl_c_ext_fp64_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp64_local_atomic_add)
-+
-+#endif // cl_ext_float_atomics
-+
- // atomic_store()
- 
- #if defined(__opencl_c_atomic_scope_device) &&                                 \
-diff --git a/clang/test/Headers/opencl-c-header.cl b/clang/test/Headers/opencl-c-header.cl
-index 2716076acdcf..7f720cf28142 100644
---- a/clang/test/Headers/opencl-c-header.cl
-+++ b/clang/test/Headers/opencl-c-header.cl
-@@ -98,3 +98,99 @@ global atomic_int z = ATOMIC_VAR_INIT(99);
- #pragma OPENCL EXTENSION cl_intel_planar_yuv : enable
- 
- // CHECK-MOD: Reading modules
-+
-+// For SPIR all extensions are supported.
-+#if defined(__SPIR__)
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+
-+#if __opencl_c_ext_fp16_global_atomic_load_store != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_load_store"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_load_store != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_load_store"
-+#endif
-+#if __opencl_c_ext_fp16_global_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp32_global_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_global_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp64_global_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp64_global_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp32_local_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_local_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp64_local_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp64_local_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp16_global_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp32_global_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_global_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp64_global_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp64_global_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp32_local_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_local_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp64_local_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp64_local_atomic_min_max"
-+#endif
-+#else
-+
-+#ifdef __opencl_c_ext_fp16_global_atomic_load_store
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_load_store defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_load_store
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_load_store defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp32_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp64_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp32_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp64_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp32_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp64_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp32_local_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp64_local_atomic_min_max defined"
-+#endif
-+
-+#endif //(defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+
-+#endif // defined(__SPIR__)
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0008-ispc-10_0_9_0_fix_for_1767.patch

@@ -1,96 +0,0 @@
-From 294ca2fd69a077b35acec9d498120d6cb0324dae Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 11:53:27 +0800
-Subject: [PATCH 1/2] This patch is required to fix the crash referenced to in
- #1767
-
-It is a port of the following llvm 11.0 commit : https://reviews.llvm.org/D76994.
-
-Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/41f13f1f64d2074ae7512fb23656c22585e912bd]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- .../CodeGen/SelectionDAG/LegalizeTypes.cpp    |  3 +-
- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 31 ++++++++++++-------
- 2 files changed, 21 insertions(+), 13 deletions(-)
-
-diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
-index 63ddb59fce68..822da2183269 100644
---- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
-+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
-@@ -173,7 +173,7 @@ void DAGTypeLegalizer::PerformExpensiveChecks() {
-       }
-     }
-   }
--
-+#ifndef NDEBUG
-   // Checked that NewNodes are only used by other NewNodes.
-   for (unsigned i = 0, e = NewNodes.size(); i != e; ++i) {
-     SDNode *N = NewNodes[i];
-@@ -181,6 +181,7 @@ void DAGTypeLegalizer::PerformExpensiveChecks() {
-          UI != UE; ++UI)
-       assert(UI->getNodeId() == NewNode && "NewNode used by non-NewNode!");
-   }
-+#endif
- }
- 
- /// This is the main entry point for the type legalizer. This does a top-down
-diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
-index faae14444d51..b908c5c58e9f 100644
---- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
-+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
-@@ -155,7 +155,9 @@ private:
-   const SDValue &getSDValue(TableId &Id) {
-     RemapId(Id);
-     assert(Id && "TableId should be non-zero");
--    return IdToValueMap[Id];
-+    auto I = IdToValueMap.find(Id);
-+    assert(I != IdToValueMap.end() && "cannot find Id in map");
-+    return I->second;
-   }
- 
- public:
-@@ -172,24 +174,29 @@ public:
-   bool run();
- 
-   void NoteDeletion(SDNode *Old, SDNode *New) {
-+    assert(Old != New && "node replaced with self");
-     for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
-       TableId NewId = getTableId(SDValue(New, i));
-       TableId OldId = getTableId(SDValue(Old, i));
- 
--      if (OldId != NewId)
-+      if (OldId != NewId) {
-         ReplacedValues[OldId] = NewId;
- 
--      // Delete Node from tables.
-+        // Delete Node from tables.  We cannot do this when OldId == NewId,
-+        // because NewId can still have table references to it in
-+        // ReplacedValues.
-+        IdToValueMap.erase(OldId);
-+        PromotedIntegers.erase(OldId);
-+        ExpandedIntegers.erase(OldId);
-+        SoftenedFloats.erase(OldId);
-+        PromotedFloats.erase(OldId);
-+        ExpandedFloats.erase(OldId);
-+        ScalarizedVectors.erase(OldId);
-+        SplitVectors.erase(OldId);
-+        WidenedVectors.erase(OldId);
-+      }
-+
-       ValueToIdMap.erase(SDValue(Old, i));
--      IdToValueMap.erase(OldId);
--      PromotedIntegers.erase(OldId);
--      ExpandedIntegers.erase(OldId);
--      SoftenedFloats.erase(OldId);
--      PromotedFloats.erase(OldId);
--      ExpandedFloats.erase(OldId);
--      ScalarizedVectors.erase(OldId);
--      SplitVectors.erase(OldId);
--      WidenedVectors.erase(OldId);
-     }
-   }
- 
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0009-ispc-10_0_fix_for_1788.patch

@@ -1,105 +0,0 @@
-From d266087e8dba9e8fd4984e1cb85c20376e2c8ea3 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 11:56:01 +0800
-Subject: [PATCH 2/2] This patch is a fix for #1788.
-
-It is a port of the following llvm 11.0 commit: https://reviews.llvm.org/D81698
-This also needed part of another llvm 11.0 commit: https://reviews.llvm.org/D72975
-
-Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/aeb50448019ce1b1002f3781f9647d486320d83c]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/include/llvm/IR/PatternMatch.h           | 22 ++++++++++++---
- .../InstCombine/InstructionCombining.cpp      | 27 +++++++++++++++++--
- 2 files changed, 44 insertions(+), 5 deletions(-)
-
-diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h
-index 6621fc9f819c..fb7ad93519f6 100644
---- a/llvm/include/llvm/IR/PatternMatch.h
-+++ b/llvm/include/llvm/IR/PatternMatch.h
-@@ -152,8 +152,10 @@ inline match_combine_and<LTy, RTy> m_CombineAnd(const LTy &L, const RTy &R) {
- 
- struct apint_match {
-   const APInt *&Res;
-+  bool AllowUndef;
- 
--  apint_match(const APInt *&R) : Res(R) {}
-+  apint_match(const APInt *&Res, bool AllowUndef)
-+    : Res(Res), AllowUndef(AllowUndef) {}
- 
-   template <typename ITy> bool match(ITy *V) {
-     if (auto *CI = dyn_cast<ConstantInt>(V)) {
-@@ -162,7 +164,8 @@ struct apint_match {
-     }
-     if (V->getType()->isVectorTy())
-       if (const auto *C = dyn_cast<Constant>(V))
--        if (auto *CI = dyn_cast_or_null<ConstantInt>(C->getSplatValue())) {
-+       if (auto *CI = dyn_cast_or_null<ConstantInt>(
-+                C->getSplatValue(AllowUndef))) {
-           Res = &CI->getValue();
-           return true;
-         }
-@@ -192,7 +195,20 @@ struct apfloat_match {
- 
- /// Match a ConstantInt or splatted ConstantVector, binding the
- /// specified pointer to the contained APInt.
--inline apint_match m_APInt(const APInt *&Res) { return Res; }
-+inline apint_match m_APInt(const APInt *&Res) {
-+  // Forbid undefs by default to maintain previous behavior.
-+  return apint_match(Res, /* AllowUndef */ false);
-+}
-+
-+/// Match APInt while allowing undefs in splat vector constants.
-+inline apint_match m_APIntAllowUndef(const APInt *&Res) {
-+  return apint_match(Res, /* AllowUndef */ true);
-+}
-+
-+/// Match APInt while forbidding undefs in splat vector constants.
-+inline apint_match m_APIntForbidUndef(const APInt *&Res) {
-+  return apint_match(Res, /* AllowUndef */ false);
-+}
- 
- /// Match a ConstantFP or splatted ConstantVector, binding the
- /// specified pointer to the contained APFloat.
-diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
-index bf32996d96e2..40a246b9d7a7 100644
---- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
-+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
-@@ -925,8 +925,31 @@ Instruction *InstCombiner::FoldOpIntoSelect(Instruction &Op, SelectInst *SI) {
-   if (auto *CI = dyn_cast<CmpInst>(SI->getCondition())) {
-     if (CI->hasOneUse()) {
-       Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
--      if ((SI->getOperand(1) == Op0 && SI->getOperand(2) == Op1) ||
--          (SI->getOperand(2) == Op0 && SI->getOperand(1) == Op1))
-+
-+      // FIXME: This is a hack to avoid infinite looping with min/max patterns.
-+      //        We have to ensure that vector constants that only differ with
-+      //        undef elements are treated as equivalent.
-+      auto areLooselyEqual = [](Value *A, Value *B) {
-+        if (A == B)
-+          return true;
-+
-+        // Test for vector constants.
-+        Constant *ConstA, *ConstB;
-+        if (!match(A, m_Constant(ConstA)) || !match(B, m_Constant(ConstB)))
-+          return false;
-+
-+        // TODO: Deal with FP constants?
-+        if (!A->getType()->isIntOrIntVectorTy() || A->getType() != B->getType())
-+          return false;
-+
-+        // Compare for equality including undefs as equal.
-+        auto *Cmp = ConstantExpr::getCompare(ICmpInst::ICMP_EQ, ConstA, ConstB);
-+        const APInt *C;
-+        return match(Cmp, m_APIntAllowUndef(C)) && C->isOneValue();
-+      };
-+
-+      if ((areLooselyEqual(TV, Op0) && areLooselyEqual(FV, Op1)) ||
-+          (areLooselyEqual(FV, Op0) && areLooselyEqual(TV, Op1)))
-         return nullptr;
-     }
-   }
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0010-ispc-10_0_fix_for_1793.patch

@@ -1,43 +0,0 @@
-From 8f83e2b7618da7a98a30839a8f41a6dd82dec468 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 12:00:23 +0800
-Subject: [PATCH 1/2] This patch is required to fix stability problem #1793
-
-It's backport of the following llvm 11.0 commit: 120c5f1057dc50229f73bc75bbabf4df6ee50fef
-
-Upstream-Status: Backport
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-index 2476fd26f250..2743acc89bca 100644
---- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-@@ -10702,8 +10702,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND_VECTOR_INREG(SDNode *N) {
-   SDValue N0 = N->getOperand(0);
-   EVT VT = N->getValueType(0);
- 
-+  // zext_vector_inreg(undef) = 0 because the top bits will be zero.
-   if (N0.isUndef())
--    return DAG.getUNDEF(VT);
-+    return DAG.getConstant(0, SDLoc(N), VT);
- 
-   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
-     return Res;
-@@ -10718,8 +10719,9 @@ SDValue DAGCombiner::visitZERO_EXTEND_VECTOR_INREG(SDNode *N) {
-   SDValue N0 = N->getOperand(0);
-   EVT VT = N->getValueType(0);
- 
-+  // sext_vector_inreg(undef) = 0 because the top bit will all be the same.
-   if (N0.isUndef())
--    return DAG.getUNDEF(VT);
-+    return DAG.getConstant(0, SDLoc(N), VT);
- 
-   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
-     return Res;
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0011-ispc-10_0_fix_for_1844.patch

@@ -1,34 +0,0 @@
-From 62b05a69b4a185cd0b7535f19742686e19fcaf22 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 12:02:37 +0800
-Subject: [PATCH 2/2] Fix for #1844, affects avx512skx-i8x64 and
- avx512skx-i16x32.
-
-It's a port of 11.0 commit edcfb47ff6d5562e22207f364c65f84302aa346b
-https://reviews.llvm.org/D76312
-
-Upstream-Status: Backport
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-index 2743acc89bca..439a8367dabe 100644
---- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-@@ -10841,7 +10841,9 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
- 
-   // Attempt to pre-truncate BUILD_VECTOR sources.
-   if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
--      TLI.isTruncateFree(SrcVT.getScalarType(), VT.getScalarType())) {
-+      TLI.isTruncateFree(SrcVT.getScalarType(), VT.getScalarType()) &&
-+      // Avoid creating illegal types if running after type legalizer.
-+      (!LegalTypes || TLI.isTypeLegal(VT.getScalarType()))) {
-     SDLoc DL(N);
-     EVT SVT = VT.getScalarType();
-     SmallVector<SDValue, 8> TruncOps;
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0012-ispc-10_0_i8_shuffle_avx512_i8_i16.patch

@@ -1,40 +0,0 @@
-From cc4301f82ca1bde1d438c3708de285b0ab8c72d3 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 12:07:25 +0800
-Subject: [PATCH 1/2] [X86] createVariablePermute - handle case where recursive
- createVariablePermute call fails
-
-Account for the case where a recursive createVariablePermute call with a wider vector type fails.
-
-Original test case from @craig.topper (Craig Topper)
-
-Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/6bdd63dc28208a597542b0c6bc41093f32417804]
-
-Signed-off-by: Simon Pilgrim <llvm-dev@redking.me.uk>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/Target/X86/X86ISelLowering.cpp | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
-index c8720d9ae3a6..63eb050e9b3a 100644
---- a/llvm/lib/Target/X86/X86ISelLowering.cpp
-+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
-@@ -9571,9 +9571,11 @@ static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec,
-       IndicesVT = EVT(VT).changeVectorElementTypeToInteger();
-       IndicesVec = widenSubVector(IndicesVT.getSimpleVT(), IndicesVec, false,
-                                   Subtarget, DAG, SDLoc(IndicesVec));
--      return extractSubVector(
--          createVariablePermute(VT, SrcVec, IndicesVec, DL, DAG, Subtarget), 0,
--          DAG, DL, SizeInBits);
-+      SDValue NewSrcVec =
-+          createVariablePermute(VT, SrcVec, IndicesVec, DL, DAG, Subtarget);
-+      if (NewSrcVec)
-+        return extractSubVector(NewSrcVec, 0, DAG, DL, SizeInBits);
-+      return SDValue();
-     } else if (SrcVec.getValueSizeInBits() < SizeInBits) {
-       // Widen smaller SrcVec to match VT.
-       SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec));
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch

@@ -1,61 +0,0 @@
-From 9cdff0785d5cf9effc8e922d3330311c4d3dda78 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 12:09:42 +0800
-Subject: [PATCH 2/2] This patch is needed for avx512skx-i8x64 and
- avx512skx-i16x32 targets.
-
-This is combination of two commits:
-- 0cd6712a7af0fa2702b5d4cc733500eb5e62e7d0 - stability fix.
-- d8ad7cc0885f32104a7cd83c77191aec15fd684f - performance follow up.
-
-Upstream-Status: Backport
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 23 +++++++++++++++++--
- 1 file changed, 21 insertions(+), 2 deletions(-)
-
-diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-index 439a8367dabe..b1639c7f275d 100644
---- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-@@ -18471,6 +18471,26 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
- 
-   // Allow targets to opt-out.
-   EVT VT = Extract->getValueType(0);
-+
-+  // We can only create byte sized loads.
-+  if (!VT.isByteSized())
-+    return SDValue();
-+
-+  unsigned Index = ExtIdx->getZExtValue();
-+  unsigned NumElts = VT.getVectorNumElements();
-+
-+  // If the index is a multiple of the extract element count, we can offset the
-+  // address by the store size multiplied by the subvector index. Otherwise if
-+  // the scalar type is byte sized, we can just use the index multiplied by
-+  // the element size in bytes as the offset.
-+  unsigned Offset;
-+  if (Index % NumElts == 0)
-+    Offset = (Index / NumElts) * VT.getStoreSize();
-+  else if (VT.getScalarType().isByteSized())
-+    Offset = Index * VT.getScalarType().getStoreSize();
-+  else
-+    return SDValue();
-+
-   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-   if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT))
-     return SDValue();
-@@ -18478,8 +18498,7 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
-   // The narrow load will be offset from the base address of the old load if
-   // we are extracting from something besides index 0 (little-endian).
-   SDLoc DL(Extract);
--  SDValue BaseAddr = Ld->getOperand(1);
--  unsigned Offset = ExtIdx->getZExtValue() * VT.getScalarType().getStoreSize();
-+  SDValue BaseAddr = Ld->getBasePtr();
- 
-   // TODO: Use "BaseIndexOffset" to make this more effective.
-   SDValue NewAddr = DAG.getMemBasePlusOffset(BaseAddr, Offset, DL);
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0014-ispc-10_0_packed_load_store_avx512skx.patch

@@ -1,97 +0,0 @@
-From c2ebd328979c081dd2c9fd0e359ed99473731d0e Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 12:13:00 +0800
-Subject: [PATCH 1/2] [X86] When storing v1i1/v2i1/v4i1 to memory, make sure we
- store zeros in the rest of the byte
-
-We can't store garbage in the unused bits. It possible that something like zextload from i1/i2/i4 is created to read the memory. Those zextloads would be legalized assuming the extra bits are 0.
-
-I'm not sure that the code in lowerStore is executed for the v1i1/v2i1/v4i1 case. It looks like the DAG combine in combineStore may have converted them to v8i1 first. And I think we're missing some cases to avoid going to the stack in the first place. But I don't have time to investigate those things at the moment so I wanted to focus on the correctness issue.
-
-Should fix PR48147.
-
-Reviewed By: RKSimon
-
-Differential Revision: https://reviews.llvm.org/D9129
-
-Upstream-Status: Backport
-
-Signed-off-by:Craig Topper <craig.topper@sifive.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/Target/X86/X86ISelLowering.cpp | 20 ++++++++++++++------
- llvm/lib/Target/X86/X86InstrAVX512.td   |  2 --
- 2 files changed, 14 insertions(+), 8 deletions(-)
-
-diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
-index 63eb050e9b3a..96b5e2cfbd82 100644
---- a/llvm/lib/Target/X86/X86ISelLowering.cpp
-+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
-@@ -22688,17 +22688,22 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
-   // Without AVX512DQ, we need to use a scalar type for v2i1/v4i1/v8i1 stores.
-   if (StoredVal.getValueType().isVector() &&
-       StoredVal.getValueType().getVectorElementType() == MVT::i1) {
--    assert(StoredVal.getValueType().getVectorNumElements() <= 8 &&
--           "Unexpected VT");
-+    unsigned NumElts = StoredVal.getValueType().getVectorNumElements();
-+    assert(NumElts <= 8 && "Unexpected VT");
-     assert(!St->isTruncatingStore() && "Expected non-truncating store");
-     assert(Subtarget.hasAVX512() && !Subtarget.hasDQI() &&
-            "Expected AVX512F without AVX512DQI");
- 
-+    // We must pad with zeros to ensure we store zeroes to any unused bits.
-     StoredVal = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
-                             DAG.getUNDEF(MVT::v16i1), StoredVal,
-                             DAG.getIntPtrConstant(0, dl));
-     StoredVal = DAG.getBitcast(MVT::i16, StoredVal);
-     StoredVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, StoredVal);
-+    // Make sure we store zeros in the extra bits.
-+    if (NumElts < 8)
-+      StoredVal = DAG.getZeroExtendInReg(StoredVal, dl,
-+                                         MVT::getIntegerVT(NumElts));
- 
-     return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
-                         St->getPointerInfo(), St->getAlignment(),
-@@ -41585,8 +41590,10 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
- 
-     EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), VT.getVectorNumElements());
-     StoredVal = DAG.getBitcast(NewVT, StoredVal);
--
--    return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
-+    SDValue Val = StoredVal.getOperand(0);
-+    // We must store zeros to the unused bits.
-+    Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1);
-+    return DAG.getStore(St->getChain(), dl, Val, St->getBasePtr(),
-                         St->getPointerInfo(), St->getAlignment(),
-                         St->getMemOperand()->getFlags());
-   }
-@@ -41602,10 +41609,11 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
-   }
- 
-   // Widen v2i1/v4i1 stores to v8i1.
--  if ((VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
-+  if ((VT == MVT::v1i1 || VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
-       Subtarget.hasAVX512()) {
-     unsigned NumConcats = 8 / VT.getVectorNumElements();
--    SmallVector<SDValue, 4> Ops(NumConcats, DAG.getUNDEF(VT));
-+    // We must store zeros to the unused bits.
-+    SmallVector<SDValue, 4> Ops(NumConcats, DAG.getConstant(0, dl, VT));
-     Ops[0] = StoredVal;
-     StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
-     return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
-diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
-index 32f012033fb0..d3b92183f87b 100644
---- a/llvm/lib/Target/X86/X86InstrAVX512.td
-+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
-@@ -2888,8 +2888,6 @@ def : Pat<(i64 (bitconvert (v64i1 VK64:$src))),
- 
- // Load/store kreg
- let Predicates = [HasDQI] in {
--  def : Pat<(store VK1:$src, addr:$dst),
--            (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
- 
-   def : Pat<(v1i1 (load addr:$src)),
-             (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK1)>;
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0015-ispc-10_0_vXi1calling_avx512_i8_i16.patch

@@ -1,173 +0,0 @@
-From c1565af764adceca118daad0f592e5f14c2bdd4a Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 12:15:09 +0800
-Subject: [PATCH 2/2] [X86] Convert vXi1 vectors to xmm/ymm/zmm types via
- getRegisterTypeForCallingConv rather than using CCPromoteToType in the td
- file
-
-    Previously we tried to promote these to xmm/ymm/zmm by promoting
-    in the X86CallingConv.td file. But this breaks when we run out
-    of xmm/ymm/zmm registers and need to fall back to memory. We end
-    up trying to create a non-sensical scalar to vector. This lead
-    to an assertion. The new tests in avx512-calling-conv.ll all
-    trigger this assertion.
-
-    Since we really want to treat these types like we do on avx2,
-    it seems better to promote them before the calling convention
-    code gets involved. Except when the calling convention is one
-    that passes the vXi1 type in a k register.
-
-    The changes in avx512-regcall-Mask.ll are because we indicated
-    that xmm/ymm/zmm types should be passed indirectly for the
-    Win64 ABI before we go to the common lines that promoted the
-    vXi1 types. This caused the promoted types to be picked up by
-    the default calling convention code. Now we promote them earlier
-    so they get passed indirectly as though they were xmm/ymm/zmm.
-
-    Differential Revision: https://reviews.llvm.org/D75154
-
-Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/eadea7868f5b7542ee6bdcd9a975697a0c919ffc]
-
-Signed-off-by:Craig Topper <craig.topper@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/Target/X86/X86ISelLowering.cpp | 90 +++++++++++++++++--------
- 1 file changed, 61 insertions(+), 29 deletions(-)
-
-diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
-index 96b5e2cfbd82..d5de94aeb8a2 100644
---- a/llvm/lib/Target/X86/X86ISelLowering.cpp
-+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
-@@ -2085,51 +2085,83 @@ X86TargetLowering::getPreferredVectorAction(MVT VT) const {
-   return TargetLoweringBase::getPreferredVectorAction(VT);
- }
- 
-+static std::pair<MVT, unsigned>
-+handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
-+                                 const X86Subtarget &Subtarget) {
-+  // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
-+  // convention is one that uses k registers.
-+  if (NumElts == 2)
-+    return {MVT::v2i64, 1};
-+  if (NumElts == 4)
-+    return {MVT::v4i32, 1};
-+  if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
-+      CC != CallingConv::Intel_OCL_BI)
-+    return {MVT::v8i16, 1};
-+  if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
-+      CC != CallingConv::Intel_OCL_BI)
-+    return {MVT::v16i8, 1};
-+  // v32i1 passes in ymm unless we have BWI and the calling convention is
-+  // regcall.
-+  if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
-+    return {MVT::v32i8, 1};
-+  // Split v64i1 vectors if we don't have v64i8 available.
-+  if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
-+    if (Subtarget.useAVX512Regs())
-+      return {MVT::v64i8, 1};
-+    return {MVT::v32i8, 2};
-+  }
-+
-+  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
-+  if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
-+      NumElts > 64)
-+    return {MVT::i8, NumElts};
-+
-+  return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
-+}
-+
- MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
-                                                      CallingConv::ID CC,
-                                                      EVT VT) const {
--  // v32i1 vectors should be promoted to v32i8 to match avx2.
--  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
--    return MVT::v32i8;
--  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
-   if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
--      Subtarget.hasAVX512() &&
--      (!isPowerOf2_32(VT.getVectorNumElements()) ||
--       (VT.getVectorNumElements() > 16 && !Subtarget.hasBWI()) ||
--       (VT.getVectorNumElements() > 64 && Subtarget.hasBWI())))
--    return MVT::i8;
--  // Split v64i1 vectors if we don't have v64i8 available.
--  if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
--      CC != CallingConv::X86_RegCall)
--    return MVT::v32i1;
-+      Subtarget.hasAVX512()) {
-+    unsigned NumElts = VT.getVectorNumElements();
-+
-+    MVT RegisterVT;
-+    unsigned NumRegisters;
-+    std::tie(RegisterVT, NumRegisters) =
-+        handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
-+    if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
-+      return RegisterVT;
-+  }
-+
-   // FIXME: Should we just make these types legal and custom split operations?
-   if ((VT == MVT::v32i16 || VT == MVT::v64i8) && !EnableOldKNLABI &&
-       Subtarget.useAVX512Regs() && !Subtarget.hasBWI())
-     return MVT::v16i32;
-+
-   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
- }
- 
- unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
-                                                           CallingConv::ID CC,
-                                                           EVT VT) const {
--  // v32i1 vectors should be promoted to v32i8 to match avx2.
--  if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
--    return 1;
--  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
-   if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
--      Subtarget.hasAVX512() &&
--      (!isPowerOf2_32(VT.getVectorNumElements()) ||
--       (VT.getVectorNumElements() > 16 && !Subtarget.hasBWI()) ||
--       (VT.getVectorNumElements() > 64 && Subtarget.hasBWI())))
--    return VT.getVectorNumElements();
--  // Split v64i1 vectors if we don't have v64i8 available.
--  if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
--      CC != CallingConv::X86_RegCall)
--    return 2;
-+      Subtarget.hasAVX512()) {
-+    unsigned NumElts = VT.getVectorNumElements();
-+
-+    MVT RegisterVT;
-+    unsigned NumRegisters;
-+    std::tie(RegisterVT, NumRegisters) =
-+        handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
-+    if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
-+      return NumRegisters;
-+  }
-+
-   // FIXME: Should we just make these types legal and custom split operations?
-   if ((VT == MVT::v32i16 || VT == MVT::v64i8) && !EnableOldKNLABI &&
-       Subtarget.useAVX512Regs() && !Subtarget.hasBWI())
-     return 1;
-+
-   return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
- }
- 
-@@ -2140,8 +2172,8 @@ unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
-   if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
-       Subtarget.hasAVX512() &&
-       (!isPowerOf2_32(VT.getVectorNumElements()) ||
--       (VT.getVectorNumElements() > 16 && !Subtarget.hasBWI()) ||
--       (VT.getVectorNumElements() > 64 && Subtarget.hasBWI()))) {
-+       (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
-+       VT.getVectorNumElements() > 64)) {
-     RegisterVT = MVT::i8;
-     IntermediateVT = MVT::i1;
-     NumIntermediates = VT.getVectorNumElements();
-@@ -2151,7 +2183,7 @@ unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
-   // Split v64i1 vectors if we don't have v64i8 available.
-   if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
-       CC != CallingConv::X86_RegCall) {
--    RegisterVT = MVT::v32i1;
-+    RegisterVT = MVT::v32i8;
-     IntermediateVT = MVT::v32i1;
-     NumIntermediates = 2;
-     return 2;
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0001-llvm-spirv-skip-building-tests.patch

@@ -1,51 +0,0 @@
-From 6690d77f9007ce82984dc1b6ae12585cb3e04785 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Wed, 21 Aug 2019 14:35:31 +0800
-Subject: [PATCH 1/2] llvm-spirv: skip building tests
-
-Some of these need clang to be built and since we're building this in-tree,
-that leads to problems when compiling libcxx, compiler-rt which aren't built
-in-tree.
-
-Instead of using SPIRV_SKIP_CLANG_BUILD to skip clang build and adding this to
-all components, disable the building of tests altogether.
-
-Upstream-Status: Inappropriate
-
-Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- CMakeLists.txt | 10 ----------
- 1 file changed, 10 deletions(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index ec61fb95..d723c0a5 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -26,13 +26,6 @@ if(LLVM_SPIRV_BUILD_EXTERNAL)
-   set(CMAKE_CXX_STANDARD 14)
-   set(CMAKE_CXX_STANDARD_REQUIRED ON)
- 
--  if(LLVM_SPIRV_INCLUDE_TESTS)
--    set(LLVM_TEST_COMPONENTS
--      llvm-as
--      llvm-dis
--    )
--  endif(LLVM_SPIRV_INCLUDE_TESTS)
--
-   find_package(LLVM ${BASE_LLVM_VERSION} REQUIRED
-     COMPONENTS
-       Analysis
-@@ -65,9 +58,6 @@ set(LLVM_SPIRV_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/include)
- 
- add_subdirectory(lib/SPIRV)
- add_subdirectory(tools/llvm-spirv)
--if(LLVM_SPIRV_INCLUDE_TESTS)
--  add_subdirectory(test)
--endif(LLVM_SPIRV_INCLUDE_TESTS)
- 
- install(
-   FILES
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0002-Add-support-for-cl_ext_float_atomics-in-SPIRVWriter.patch

@@ -1,433 +0,0 @@
-From 8e12d8fb3cdbdafca73fe8ed4f0cde773b1788b4 Mon Sep 17 00:00:00 2001
-From: haonanya <haonan.yang@intel.com>
-Date: Wed, 28 Jul 2021 11:43:20 +0800
-Subject: [PATCH 2/2] Add support for cl_ext_float_atomics in SPIRVWriter
-
-Upstream-Status: Backport [Taken from opencl-clang patches, https://github.com/intel/opencl-clang/blob/ocl-open-110/patches/spirv/0001-Add-support-for-cl_ext_float_atomics-in-SPIRVWriter.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- lib/SPIRV/OCLToSPIRV.cpp                | 80 +++++++++++++++++++++++--
- lib/SPIRV/OCLUtil.cpp                   | 26 --------
- lib/SPIRV/OCLUtil.h                     |  4 --
- test/negative/InvalidAtomicBuiltins.cl  | 12 +---
- test/transcoding/AtomicFAddEXTForOCL.ll | 64 ++++++++++++++++++++
- test/transcoding/AtomicFMaxEXTForOCL.ll | 64 ++++++++++++++++++++
- test/transcoding/AtomicFMinEXTForOCL.ll | 64 ++++++++++++++++++++
- 7 files changed, 269 insertions(+), 45 deletions(-)
- create mode 100644 test/transcoding/AtomicFAddEXTForOCL.ll
- create mode 100644 test/transcoding/AtomicFMaxEXTForOCL.ll
- create mode 100644 test/transcoding/AtomicFMinEXTForOCL.ll
-
-diff --git a/lib/SPIRV/OCLToSPIRV.cpp b/lib/SPIRV/OCLToSPIRV.cpp
-index 04d51586..f00f5f7b 100644
---- a/lib/SPIRV/OCLToSPIRV.cpp
-+++ b/lib/SPIRV/OCLToSPIRV.cpp
-@@ -421,10 +421,63 @@ void OCLToSPIRVBase::visitCallInst(CallInst &CI) {
-   if (DemangledName.find(kOCLBuiltinName::AtomicPrefix) == 0 ||
-       DemangledName.find(kOCLBuiltinName::AtomPrefix) == 0) {
- 
--    // Compute atomic builtins do not support floating types.
--    if (CI.getType()->isFloatingPointTy() &&
--        isComputeAtomicOCLBuiltin(DemangledName))
--      return;
-+    // Compute "atom" prefixed builtins do not support floating types.
-+    if (CI.getType()->isFloatingPointTy()) {
-+      if (DemangledName.find(kOCLBuiltinName::AtomPrefix) == 0)
-+        return;
-+      // handle functions which are "atomic_" prefixed.
-+      StringRef Stem = DemangledName;
-+      Stem = Stem.drop_front(strlen("atomic_"));
-+      // FP-typed atomic_{add, sub, inc, dec, exchange, min, max, or, and, xor,
-+      // fetch_or, fetch_xor, fetch_and, fetch_or_explicit, fetch_xor_explicit,
-+      // fetch_and_explicit} should be identified as function call
-+      bool IsFunctionCall = llvm::StringSwitch<bool>(Stem)
-+                                .Case("add", true)
-+                                .Case("sub", true)
-+                                .Case("inc", true)
-+                                .Case("dec", true)
-+                                .Case("cmpxchg", true)
-+                                .Case("min", true)
-+                                .Case("max", true)
-+                                .Case("or", true)
-+                                .Case("xor", true)
-+                                .Case("and", true)
-+                                .Case("fetch_or", true)
-+                                .Case("fetch_and", true)
-+                                .Case("fetch_xor", true)
-+                                .Case("fetch_or_explicit", true)
-+                                .Case("fetch_xor_explicit", true)
-+                                .Case("fetch_and_explicit", true)
-+                                .Default(false);
-+      if (IsFunctionCall)
-+        return;
-+      if (F->arg_size() != 2) {
-+        IsFunctionCall = llvm::StringSwitch<bool>(Stem)
-+                             .Case("exchange", true)
-+                             .Case("fetch_add", true)
-+                             .Case("fetch_sub", true)
-+                             .Case("fetch_min", true)
-+                             .Case("fetch_max", true)
-+                             .Case("load", true)
-+                             .Case("store", true)
-+                             .Default(false);
-+        if (IsFunctionCall)
-+          return;
-+      }
-+      if (F->arg_size() != 3 && F->arg_size() != 4) {
-+        IsFunctionCall = llvm::StringSwitch<bool>(Stem)
-+                             .Case("exchange_explicit", true)
-+                             .Case("fetch_add_explicit", true)
-+                             .Case("fetch_sub_explicit", true)
-+                             .Case("fetch_min_explicit", true)
-+                             .Case("fetch_max_explicit", true)
-+                             .Case("load_explicit", true)
-+                             .Case("store_explicit", true)
-+                             .Default(false);
-+        if (IsFunctionCall)
-+          return;
-+      }
-+    }
- 
-     auto PCI = &CI;
-     if (DemangledName == kOCLBuiltinName::AtomicInit) {
-@@ -839,7 +892,7 @@ void OCLToSPIRVBase::transAtomicBuiltin(CallInst *CI,
-   AttributeList Attrs = CI->getCalledFunction()->getAttributes();
-   mutateCallInstSPIRV(
-       M, CI,
--      [=](CallInst *CI, std::vector<Value *> &Args) {
-+      [=](CallInst *CI, std::vector<Value *> &Args) -> std::string {
-         Info.PostProc(Args);
-         // Order of args in OCL20:
-         // object, 0-2 other args, 1-2 order, scope
-@@ -868,7 +921,22 @@ void OCLToSPIRVBase::transAtomicBuiltin(CallInst *CI,
-           std::rotate(Args.begin() + 2, Args.begin() + OrderIdx,
-                       Args.end() - Offset);
-         }
--        return getSPIRVFuncName(OCLSPIRVBuiltinMap::map(Info.UniqName));
-+
-+        llvm::Type* AtomicBuiltinsReturnType =
-+            CI->getCalledFunction()->getReturnType();
-+        auto IsFPType = [](llvm::Type *ReturnType) {
-+          return ReturnType->isHalfTy() || ReturnType->isFloatTy() ||
-+                 ReturnType->isDoubleTy();
-+        };
-+        auto SPIRVFunctionName =
-+            getSPIRVFuncName(OCLSPIRVBuiltinMap::map(Info.UniqName));
-+        if (!IsFPType(AtomicBuiltinsReturnType))
-+          return SPIRVFunctionName;
-+        // Translate FP-typed atomic builtins.
-+        return llvm::StringSwitch<std::string>(SPIRVFunctionName)
-+            .Case("__spirv_AtomicIAdd", "__spirv_AtomicFAddEXT")
-+            .Case("__spirv_AtomicSMax", "__spirv_AtomicFMaxEXT")
-+            .Case("__spirv_AtomicSMin", "__spirv_AtomicFMinEXT");
-       },
-       &Attrs);
- }
-diff --git a/lib/SPIRV/OCLUtil.cpp b/lib/SPIRV/OCLUtil.cpp
-index 2de3f152..85155e39 100644
---- a/lib/SPIRV/OCLUtil.cpp
-+++ b/lib/SPIRV/OCLUtil.cpp
-@@ -662,32 +662,6 @@ size_t getSPIRVAtomicBuiltinNumMemoryOrderArgs(Op OC) {
-   return 1;
- }
- 
--bool isComputeAtomicOCLBuiltin(StringRef DemangledName) {
--  if (!DemangledName.startswith(kOCLBuiltinName::AtomicPrefix) &&
--      !DemangledName.startswith(kOCLBuiltinName::AtomPrefix))
--    return false;
--
--  return llvm::StringSwitch<bool>(DemangledName)
--      .EndsWith("add", true)
--      .EndsWith("sub", true)
--      .EndsWith("inc", true)
--      .EndsWith("dec", true)
--      .EndsWith("cmpxchg", true)
--      .EndsWith("min", true)
--      .EndsWith("max", true)
--      .EndsWith("and", true)
--      .EndsWith("or", true)
--      .EndsWith("xor", true)
--      .EndsWith("add_explicit", true)
--      .EndsWith("sub_explicit", true)
--      .EndsWith("or_explicit", true)
--      .EndsWith("xor_explicit", true)
--      .EndsWith("and_explicit", true)
--      .EndsWith("min_explicit", true)
--      .EndsWith("max_explicit", true)
--      .Default(false);
--}
--
- BarrierLiterals getBarrierLiterals(CallInst *CI) {
-   auto N = CI->getNumArgOperands();
-   assert(N == 1 || N == 2);
-diff --git a/lib/SPIRV/OCLUtil.h b/lib/SPIRV/OCLUtil.h
-index 4c05c672..c8577e9b 100644
---- a/lib/SPIRV/OCLUtil.h
-+++ b/lib/SPIRV/OCLUtil.h
-@@ -394,10 +394,6 @@ size_t getAtomicBuiltinNumMemoryOrderArgs(StringRef Name);
- /// Get number of memory order arguments for spirv atomic builtin function.
- size_t getSPIRVAtomicBuiltinNumMemoryOrderArgs(Op OC);
- 
--/// Return true for OpenCL builtins which do compute operations
--/// (like add, sub, min, max, inc, dec, ...) atomically
--bool isComputeAtomicOCLBuiltin(StringRef DemangledName);
--
- /// Get OCL version from metadata opencl.ocl.version.
- /// \param AllowMulti Allows multiple operands if true.
- /// \return OCL version encoded as Major*10^5+Minor*10^3+Rev,
-diff --git a/test/negative/InvalidAtomicBuiltins.cl b/test/negative/InvalidAtomicBuiltins.cl
-index b8ec5b89..23dcc4e3 100644
---- a/test/negative/InvalidAtomicBuiltins.cl
-+++ b/test/negative/InvalidAtomicBuiltins.cl
-@@ -1,7 +1,9 @@
- // Check that translator doesn't generate atomic instructions for atomic builtins
- // which are not defined in the spec.
- 
--// RUN: %clang_cc1 -triple spir -O1 -cl-std=cl2.0 -fdeclare-opencl-builtins -finclude-default-header %s -emit-llvm-bc -o %t.bc
-+// To drop `fdeclare-opencl-builtins` option, since FP-typed atomic function
-+// TableGen definitions have not been introduced.
-+// RUN: %clang_cc1 -triple spir -O1 -cl-std=cl2.0 -finclude-default-header %s -emit-llvm-bc -o %t.bc
- // RUN: llvm-spirv %t.bc -spirv-text -o - | FileCheck %s
- // RUN: llvm-spirv %t.bc -o %t.spv
- // RUN: spirv-val %t.spv
-@@ -41,13 +43,9 @@ float __attribute__((overloadable)) atomic_fetch_xor(volatile generic atomic_flo
- double __attribute__((overloadable)) atomic_fetch_and(volatile generic atomic_double *object, double operand, memory_order order);
- double __attribute__((overloadable)) atomic_fetch_max(volatile generic atomic_double *object, double operand, memory_order order);
- double __attribute__((overloadable)) atomic_fetch_min(volatile generic atomic_double *object, double operand, memory_order order);
--float __attribute__((overloadable)) atomic_fetch_add_explicit(volatile generic atomic_float *object, float operand, memory_order order);
--float __attribute__((overloadable)) atomic_fetch_sub_explicit(volatile generic atomic_float *object, float operand, memory_order order);
- float __attribute__((overloadable)) atomic_fetch_or_explicit(volatile generic atomic_float *object, float operand, memory_order order);
- float __attribute__((overloadable)) atomic_fetch_xor_explicit(volatile generic atomic_float *object, float operand, memory_order order);
- double __attribute__((overloadable)) atomic_fetch_and_explicit(volatile generic atomic_double *object, double operand, memory_order order);
--double __attribute__((overloadable)) atomic_fetch_max_explicit(volatile generic atomic_double *object, double operand, memory_order order);
--double __attribute__((overloadable)) atomic_fetch_min_explicit(volatile generic atomic_double *object, double operand, memory_order order);
- 
- __kernel void test_atomic_fn(volatile __global float *p,
-                              volatile __global double *pp,
-@@ -86,11 +84,7 @@ __kernel void test_atomic_fn(volatile __global float *p,
-     d = atomic_fetch_and(pp, val, order);
-     d = atomic_fetch_min(pp, val, order);
-     d = atomic_fetch_max(pp, val, order);
--    f = atomic_fetch_add_explicit(p, val, order);
--    f = atomic_fetch_sub_explicit(p, val, order);
-     f = atomic_fetch_or_explicit(p, val, order);
-     f = atomic_fetch_xor_explicit(p, val, order);
-     d = atomic_fetch_and_explicit(pp, val, order);
--    d = atomic_fetch_min_explicit(pp, val, order);
--    d = atomic_fetch_max_explicit(pp, val, order);
- }
-diff --git a/test/transcoding/AtomicFAddEXTForOCL.ll b/test/transcoding/AtomicFAddEXTForOCL.ll
-new file mode 100644
-index 00000000..fb146fb9
---- /dev/null
-+++ b/test/transcoding/AtomicFAddEXTForOCL.ll
-@@ -0,0 +1,64 @@
-+; RUN: llvm-as %s -o %t.bc
-+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add -o %t.spv
-+; RUN: spirv-val %t.spv
-+; RUN: llvm-spirv -to-text %t.spv -o %t.spt
-+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
-+
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
-+
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
-+
-+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
-+target triple = "spir-unknown-unknown"
-+
-+; CHECK-SPIRV: Capability AtomicFloat32AddEXT
-+; CHECK-SPIRV: Capability AtomicFloat64AddEXT
-+; CHECK-SPIRV: Extension "SPV_EXT_shader_atomic_float_add"
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
-+
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_atomic_float(float addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_32]]
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_add_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call = tail call spir_func float @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)* %a, float 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func float @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)*, float, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_atomic_double(double addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_64]]
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_add_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+diid]]({{.*}})
-+  %call = tail call spir_func double @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)* %a, double 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+; Function Attrs: convergent
-+declare spir_func double @_Z25atomic_fetch_add_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)*, double, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #1 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #2 = { convergent nounwind }
-+
-+!llvm.module.flags = !{!0}
-+!opencl.ocl.version = !{!1}
-+!opencl.spir.version = !{!1}
-+!llvm.ident = !{!2}
-+
-+!0 = !{i32 1, !"wchar_size", i32 4}
-+!1 = !{i32 2, i32 0}
-+!2 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git 94aa388f0ce0723bb15503cf41c2c15b288375b9)"}
-diff --git a/test/transcoding/AtomicFMaxEXTForOCL.ll b/test/transcoding/AtomicFMaxEXTForOCL.ll
-new file mode 100644
-index 00000000..1f2530d9
---- /dev/null
-+++ b/test/transcoding/AtomicFMaxEXTForOCL.ll
-@@ -0,0 +1,64 @@
-+; RUN: llvm-as %s -o %t.bc
-+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_EXT_shader_atomic_float_min_max -o %t.spv
-+; RUN: spirv-val %t.spv
-+; RUN: llvm-spirv -to-text %t.spv -o %t.spt
-+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
-+
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
-+
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
-+
-+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
-+target triple = "spir-unknown-unknown"
-+
-+; CHECK-SPIRV: Capability AtomicFloat32MinMaxEXT
-+; CHECK-SPIRV: Capability AtomicFloat64MinMaxEXT
-+; CHECK-SPIRV: Extension "SPV_EXT_shader_atomic_float_min_max"
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_float(float addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMaxEXT [[TYPE_FLOAT_32]]
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_max_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call = tail call spir_func float @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)* %a, float 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func float @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)*, float, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_double(double addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMaxEXT [[TYPE_FLOAT_64]]
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_max_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMaxEXT[[:alnum:]]+diid]]({{.*}})
-+  %call = tail call spir_func double @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)* %a, double 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func double @_Z25atomic_fetch_max_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)*, double, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #1 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #2 = { convergent nounwind }
-+
-+!llvm.module.flags = !{!0}
-+!opencl.ocl.version = !{!1}
-+!opencl.spir.version = !{!1}
-+!llvm.ident = !{!2}
-+
-+!0 = !{i32 1, !"wchar_size", i32 4}
-+!1 = !{i32 2, i32 0}
-+!2 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git 94aa388f0ce0723bb15503cf41c2c15b288375b9)"}
-diff --git a/test/transcoding/AtomicFMinEXTForOCL.ll b/test/transcoding/AtomicFMinEXTForOCL.ll
-new file mode 100644
-index 00000000..6196b0f8
---- /dev/null
-+++ b/test/transcoding/AtomicFMinEXTForOCL.ll
-@@ -0,0 +1,64 @@
-+; RUN: llvm-as %s -o %t.bc
-+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_EXT_shader_atomic_float_min_max -o %t.spv
-+; RUN: spirv-val %t.spv
-+; RUN: llvm-spirv -to-text %t.spv -o %t.spt
-+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
-+
-+; RUN: llvm-spirv --spirv-target-env=CL2.0 -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-CL,CHECK-LLVM-CL20
-+
-+; RUN: llvm-spirv --spirv-target-env=SPV-IR -r %t.spv -o %t.rev.bc
-+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK-LLVM-SPV
-+
-+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
-+target triple = "spir-unknown-unknown"
-+
-+; CHECK-SPIRV: Capability AtomicFloat32MinMaxEXT
-+; CHECK-SPIRV: Capability AtomicFloat64MinMaxEXT
-+; CHECK-SPIRV: Extension "SPV_EXT_shader_atomic_float_min_max"
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32
-+; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_float(float addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMinEXT [[TYPE_FLOAT_32]]
-+  ; CHECK-LLVM-CL20: call spir_func float @[[FLOAT_FUNC_NAME:_Z25atomic_fetch_min_explicit[[:alnum:]]+_Atomicff[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+fiif]]({{.*}})
-+  %call = tail call spir_func float @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)* %a, float 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func float @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicff12memory_order(float addrspace(1)*, float, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+
-+; Function Attrs: convergent norecurse nounwind
-+define dso_local spir_func void @test_double(double addrspace(1)* %a) local_unnamed_addr #0 {
-+entry:
-+  ; CHECK-SPIRV: 7 AtomicFMinEXT [[TYPE_FLOAT_64]]
-+  ; CHECK-LLVM-CL20: call spir_func double @[[DOUBLE_FUNC_NAME:_Z25atomic_fetch_min_explicit[[:alnum:]]+_Atomicdd[a-zA-Z0-9_]+]]({{.*}})
-+  ; CHECK-LLVM-SPV: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFMinEXT[[:alnum:]]+diid]]({{.*}})
-+  %call = tail call spir_func double @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)* %a, double 0.000000e+00, i32 0) #2
-+  ret void
-+}
-+
-+; Function Attrs: convergent
-+declare spir_func double @_Z25atomic_fetch_min_explicitPU3AS1VU7_Atomicdd12memory_order(double addrspace(1)*, double, i32) local_unnamed_addr #1
-+; CHECK-LLVM-SPV: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+; CHECK-LLVM-CL: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float
-+; CHECK-LLVM-CL: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double
-+
-+attributes #0 = { convergent norecurse nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #1 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-+attributes #2 = { convergent nounwind }
-+
-+!llvm.module.flags = !{!0}
-+!opencl.ocl.version = !{!1}
-+!opencl.spir.version = !{!1}
-+!llvm.ident = !{!2}
-+
-+!0 = !{i32 1, !"wchar_size", i32 4}
-+!1 = !{i32 2, i32 0}
-+!2 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git 94aa388f0ce0723bb15503cf41c2c15b288375b9)"}
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0002-Memory-leak-fix-for-Managed-Static-Mutex.patch

@@ -1,35 +0,0 @@
-From ef27f1f99ad661c9604b7ff10efb1122466c508b Mon Sep 17 00:00:00 2001
-From: juanrod2 <>
-Date: Tue, 22 Dec 2020 08:33:08 +0800
-Subject: [PATCH 2/6] Memory leak fix for Managed Static Mutex
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-100/patches/llvm/0001-Memory-leak-fix-for-Managed-Static-Mutex.patch]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
-
-Cleaning a mutex inside ManagedStatic llvm class.
----
- llvm/lib/Support/ManagedStatic.cpp | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/llvm/lib/Support/ManagedStatic.cpp b/llvm/lib/Support/ManagedStatic.cpp
-index 053493f72fb5..6571580ccecf 100644
---- a/llvm/lib/Support/ManagedStatic.cpp
-+++ b/llvm/lib/Support/ManagedStatic.cpp
-@@ -76,8 +76,12 @@ void ManagedStaticBase::destroy() const {
- 
- /// llvm_shutdown - Deallocate and destroy all ManagedStatic variables.
- void llvm::llvm_shutdown() {
--  std::lock_guard<std::recursive_mutex> Lock(*getManagedStaticMutex());
-+  getManagedStaticMutex()->lock();
- 
-   while (StaticList)
-     StaticList->destroy();
-+
-+  getManagedStaticMutex()->unlock();
-+  delete ManagedStaticMutex;
-+  ManagedStaticMutex = nullptr;
- }
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0003-Remove-repo-name-in-LLVM-IR.patch

@@ -1,49 +0,0 @@
-From a71ab6fb04b918b856f1dd802cfdb4a7ccd53290 Mon Sep 17 00:00:00 2001
-From: Feng Zou <feng.zou@intel.com>
-Date: Tue, 20 Oct 2020 11:29:04 +0800
-Subject: [PATCH 3/6] Remove repo name in LLVM IR
-
-Upstream-Status: Backport [Taken from opencl-clang patches, https://github.com/intel/opencl-clang/blob/ocl-open-110/patches/llvm/0002-Remove-repo-name-in-LLVM-IR.patch]
-Signed-off-by: Feng Zou <feng.zou@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/cmake/modules/VersionFromVCS.cmake | 23 ++++++++++++-----------
- 1 file changed, 12 insertions(+), 11 deletions(-)
-
-diff --git a/llvm/cmake/modules/VersionFromVCS.cmake b/llvm/cmake/modules/VersionFromVCS.cmake
-index 18edbeabe3e4..2d9652634787 100644
---- a/llvm/cmake/modules/VersionFromVCS.cmake
-+++ b/llvm/cmake/modules/VersionFromVCS.cmake
-@@ -33,17 +33,18 @@ function(get_source_info path revision repository)
-       else()
-         set(remote "origin")
-       endif()
--      execute_process(COMMAND ${GIT_EXECUTABLE} remote get-url ${remote}
--        WORKING_DIRECTORY ${path}
--        RESULT_VARIABLE git_result
--        OUTPUT_VARIABLE git_output
--        ERROR_QUIET)
--      if(git_result EQUAL 0)
--        string(STRIP "${git_output}" git_output)
--        set(${repository} ${git_output} PARENT_SCOPE)
--      else()
--        set(${repository} ${path} PARENT_SCOPE)
--      endif()
-+      # Do not show repo name in IR
-+      # execute_process(COMMAND ${GIT_EXECUTABLE} remote get-url ${remote}
-+      #   WORKING_DIRECTORY ${path}
-+      #   RESULT_VARIABLE git_result
-+      #   OUTPUT_VARIABLE git_output
-+      #   ERROR_QUIET)
-+      # if(git_result EQUAL 0)
-+      #   string(STRIP "${git_output}" git_output)
-+      #   set(${repository} ${git_output} PARENT_SCOPE)
-+      # else()
-+      #   set(${repository} ${path} PARENT_SCOPE)
-+      # endif()
-     endif()
-   else()
-     message(WARNING "Git not found. Version cannot be determined.")
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0004-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch

@@ -1,51 +0,0 @@
-From 546d9089fe5e21cccc671a0a89555cd4d5f8c817 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Thu, 19 Aug 2021 15:52:24 +0800
-Subject: [PATCH 4/6] Remove __IMAGE_SUPPORT__ macro for SPIR since SPIR
- doesn't require image support
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-110/patches/clang/0002-Remove-__IMAGE_SUPPORT__-macro-for-SPIR.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/Frontend/InitPreprocessor.cpp     | 3 ---
- clang/test/Preprocessor/predefined-macros.c | 2 --
- 2 files changed, 5 deletions(-)
-
-diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp
-index 5bb489c11909..cf3b48cb65d2 100644
---- a/clang/lib/Frontend/InitPreprocessor.cpp
-+++ b/clang/lib/Frontend/InitPreprocessor.cpp
-@@ -1115,9 +1115,6 @@ static void InitializePredefinedMacros(const TargetInfo &TI,
-   if (TI.getSupportedOpenCLOpts().isSupported(#Ext))                           \
-     Builder.defineMacro(#Ext);
- #include "clang/Basic/OpenCLExtensions.def"
--
--    if (TI.getTriple().isSPIR())
--      Builder.defineMacro("__IMAGE_SUPPORT__");
-   }
- 
-   if (TI.hasInt128Type() && LangOpts.CPlusPlus && LangOpts.GNUMode) {
-diff --git a/clang/test/Preprocessor/predefined-macros.c b/clang/test/Preprocessor/predefined-macros.c
-index 6c80517ec4d4..b5e5d7e2d546 100644
---- a/clang/test/Preprocessor/predefined-macros.c
-+++ b/clang/test/Preprocessor/predefined-macros.c
-@@ -186,14 +186,12 @@
- 
- // RUN: %clang_cc1 %s -E -dM -o - -x cl -triple spir-unknown-unknown \
- // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SPIR
--// CHECK-SPIR-DAG: #define __IMAGE_SUPPORT__ 1
- // CHECK-SPIR-DAG: #define __SPIR__ 1
- // CHECK-SPIR-DAG: #define __SPIR32__ 1
- // CHECK-SPIR-NOT: #define __SPIR64__ 1
- 
- // RUN: %clang_cc1 %s -E -dM -o - -x cl -triple spir64-unknown-unknown \
- // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SPIR64
--// CHECK-SPIR64-DAG: #define __IMAGE_SUPPORT__ 1
- // CHECK-SPIR64-DAG: #define __SPIR__ 1
- // CHECK-SPIR64-DAG: #define __SPIR64__ 1
- // CHECK-SPIR64-NOT: #define __SPIR32__ 1
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0005-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch

@@ -1,52 +0,0 @@
-From 747e48959e18ac8b586078a82472a0799d12925c Mon Sep 17 00:00:00 2001
-From: Raphael Isemann <teemperor@gmail.com>
-Date: Thu, 1 Apr 2021 18:41:44 +0200
-Subject: [PATCH 5/6] Avoid calling ParseCommandLineOptions in BackendUtil if
- possible
-
-Calling `ParseCommandLineOptions` should only be called from `main` as the
-CommandLine setup code isn't thread-safe. As BackendUtil is part of the
-generic Clang FrontendAction logic, a process which has several threads executing
-Clang FrontendActions will randomly crash in the unsafe setup code.
-
-This patch avoids calling the function unless either the debug-pass option or
-limit-float-precision option is set. Without these two options set the
-`ParseCommandLineOptions` call doesn't do anything beside parsing
-the command line `clang` which doesn't set any options.
-
-See also D99652 where LLDB received a workaround for this crash.
-
-Reviewed By: JDevlieghere
-
-Differential Revision: https://reviews.llvm.org/D99740
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-110/patches/clang/0003-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/CodeGen/BackendUtil.cpp | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
-index dce0940670a2..ab478090ed1c 100644
---- a/clang/lib/CodeGen/BackendUtil.cpp
-+++ b/clang/lib/CodeGen/BackendUtil.cpp
-@@ -797,7 +797,15 @@ static void setCommandLineOpts(const CodeGenOptions &CodeGenOpts) {
-     BackendArgs.push_back("-limit-float-precision");
-     BackendArgs.push_back(CodeGenOpts.LimitFloatPrecision.c_str());
-   }
-+  // Check for the default "clang" invocation that won't set any cl::opt values.
-+  // Skip trying to parse the command line invocation to avoid the issues
-+  // described below.
-+  if (BackendArgs.size() == 1)
-+    return;
-   BackendArgs.push_back(nullptr);
-+  // FIXME: The command line parser below is not thread-safe and shares a global
-+  // state, so this call might crash or overwrite the options of another Clang
-+  // instance in the same process.
-   llvm::cl::ParseCommandLineOptions(BackendArgs.size() - 1,
-                                     BackendArgs.data());
- }
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0006-OpenCL-support-cl_ext_float_atomics.patch

@@ -1,353 +0,0 @@
-From a1b924d76cdacfa3f9dbb79a9e3edddcd75f61ca Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Thu, 19 Aug 2021 16:06:33 +0800
-Subject: [PATCH 6/6] [OpenCL] support cl_ext_float_atomics
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-110/patches/clang/0004-OpenCL-support-cl_ext_float_atomics.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/Headers/opencl-c-base.h     |  25 ++++
- clang/lib/Headers/opencl-c.h          | 195 ++++++++++++++++++++++++++
- clang/test/Headers/opencl-c-header.cl |  85 +++++++++++
- 3 files changed, 305 insertions(+)
-
-diff --git a/clang/lib/Headers/opencl-c-base.h b/clang/lib/Headers/opencl-c-base.h
-index afa900ab24d9..9a3ee8529acf 100644
---- a/clang/lib/Headers/opencl-c-base.h
-+++ b/clang/lib/Headers/opencl-c-base.h
-@@ -62,6 +62,31 @@
- #endif
- #endif // defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ == CL_VERSION_2_0)
- 
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+// For SPIR all extensions are supported.
-+#if defined(__SPIR__)
-+#define cl_ext_float_atomics
-+#ifdef cl_khr_fp16
-+#define __opencl_c_ext_fp16_global_atomic_load_store 1
-+#define __opencl_c_ext_fp16_local_atomic_load_store 1
-+#define __opencl_c_ext_fp16_global_atomic_add 1
-+#define __opencl_c_ext_fp16_local_atomic_add 1
-+#define __opencl_c_ext_fp16_global_atomic_min_max 1
-+#define __opencl_c_ext_fp16_local_atomic_min_max 1
-+#endif
-+#ifdef __opencl_c_fp64
-+#define __opencl_c_ext_fp64_global_atomic_add 1
-+#define __opencl_c_ext_fp64_local_atomic_add 1
-+#define __opencl_c_ext_fp64_global_atomic_min_max 1
-+#define __opencl_c_ext_fp64_local_atomic_min_max 1
-+#endif
-+#define __opencl_c_ext_fp32_global_atomic_add 1
-+#define __opencl_c_ext_fp32_local_atomic_add 1
-+#define __opencl_c_ext_fp32_global_atomic_min_max 1
-+#define __opencl_c_ext_fp32_local_atomic_min_max 1
-+#endif // defined(__SPIR__)
-+#endif // (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+
- // built-in scalar data types:
- 
- /**
-diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h
-index 67d900eb1c3d..bda0f5c6df80 100644
---- a/clang/lib/Headers/opencl-c.h
-+++ b/clang/lib/Headers/opencl-c.h
-@@ -14354,6 +14354,201 @@ intptr_t __ovld atomic_fetch_max_explicit(
-        // defined(cl_khr_int64_extended_atomics)
- #endif // (__OPENCL_C_VERSION__ >= CL_VERSION_3_0)
- 
-+#if defined(cl_ext_float_atomics)
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_max(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_min_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_max(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_min_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_max(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_min_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_global_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_max(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_min_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_max(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_min_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_max(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_min_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_add)
-+float __ovld atomic_fetch_add(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_sub(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_add_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_local_atomic_add)
-+float __ovld atomic_fetch_add(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_sub(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_add_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp32_local_atomic_add)
-+float __ovld atomic_fetch_add(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_sub(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_add_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+
-+#if defined(__opencl_c_ext_fp64_global_atomic_add)
-+double __ovld atomic_fetch_add(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_sub(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_add_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_local_atomic_add)
-+double __ovld atomic_fetch_add(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_sub(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_add_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp64_local_atomic_add)
-+double __ovld atomic_fetch_add(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_sub(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_add_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+
-+#endif // cl_ext_float_atomics
-+
- // atomic_store()
- 
- #if defined(__opencl_c_atomic_scope_device) &&                                 \
-diff --git a/clang/test/Headers/opencl-c-header.cl b/clang/test/Headers/opencl-c-header.cl
-index 2716076acdcf..6b3eca84e8b9 100644
---- a/clang/test/Headers/opencl-c-header.cl
-+++ b/clang/test/Headers/opencl-c-header.cl
-@@ -98,3 +98,88 @@ global atomic_int z = ATOMIC_VAR_INIT(99);
- #pragma OPENCL EXTENSION cl_intel_planar_yuv : enable
- 
- // CHECK-MOD: Reading modules
-+
-+// For SPIR all extensions are supported.
-+#if defined(__SPIR__)
-+
-+#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+
-+#if __opencl_c_ext_fp16_global_atomic_load_store != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_load_store"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_load_store != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_load_store"
-+#endif
-+#if __opencl_c_ext_fp16_global_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp32_global_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_global_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp32_local_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_local_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp16_global_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp32_global_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_global_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp32_local_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_local_atomic_min_max"
-+#endif
-+
-+#else
-+#ifdef __opencl_c_ext_fp16_global_atomic_load_store
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_load_store defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_load_store
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_load_store defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp32_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp64_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp32_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp64_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp32_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp64_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp32_local_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp64_local_atomic_min_max defined"
-+#endif
-+
-+#endif //(defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
-+
-+#endif // defined(__SPIR__)
-+
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0007-ispc-11_0_11_1_disable-A-B-A-B-in-InstCombine.patch

@@ -1,47 +0,0 @@
-From ef2b930a8e33078449737a93e7d522b2280ec58c Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 11:39:16 +0800
-Subject: [PATCH 1/2] This patch is needed for ISPC for Gen only
-
-Transformation of add to or is not safe for VC backend.
-
-Upstream-Status: Backport [Taken from ispc,https://github.com/ispc/ispc/blob/v1.16.1/llvm_patches/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- .../lib/Transforms/InstCombine/InstCombineAddSub.cpp | 12 ++++++++----
- 1 file changed, 8 insertions(+), 4 deletions(-)
-
-diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-index a7f5e0a7774d..bf02b0f70827 100644
---- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-@@ -15,6 +15,7 @@
- #include "llvm/ADT/APInt.h"
- #include "llvm/ADT/STLExtras.h"
- #include "llvm/ADT/SmallVector.h"
-+#include "llvm/ADT/Triple.h"
- #include "llvm/Analysis/InstructionSimplify.h"
- #include "llvm/Analysis/ValueTracking.h"
- #include "llvm/IR/Constant.h"
-@@ -1324,10 +1325,13 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
-       return BinaryOperator::CreateSRem(RHS, NewRHS);
-     }
-   }
--
--  // A+B --> A|B iff A and B have no bits set in common.
--  if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
--    return BinaryOperator::CreateOr(LHS, RHS);
-+  
-+  // Disable this transformation for ISPC SPIR-V
-+  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
-+    // A+B --> A|B iff A and B have no bits set in common.
-+    if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
-+      return BinaryOperator::CreateOr(LHS, RHS);
-+  }
- 
-   // FIXME: We already did a check for ConstantInt RHS above this.
-   // FIXME: Is this pattern covered by another fold? No regression tests fail on
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0008-ispc-11_0_11_1_packed_load_store_avx512.patch

@@ -1,95 +0,0 @@
-From c20838176e8bea9e5a176c59c78bbce9051ec987 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 11:41:47 +0800
-Subject: [PATCH 2/2] [X86] When storing v1i1/v2i1/v4i1 to memory, make sure we
- store zeros in the rest of the byte
-
-We can't store garbage in the unused bits. It possible that something like zextload from i1/i2/i4 is created to read the memory. Those zextloads would be legalized assuming the extra bits are 0.
-
-I'm not sure that the code in lowerStore is executed for the v1i1/v2i1/v4i1 case. It looks like the DAG combine in combineStore may have converted them to v8i1 first. And I think we're missing some cases to avoid going to the stack in the first place. But I don't have time to investigate those things at the moment so I wanted to focus on the correctness issue.
-
-Should fix PR48147.
-
-Reviewed By: RKSimon
-
-Differential Revision: https://reviews.llvm.org/D91294
-
-Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/a4124e455e641db1e18d4221d2dacb31953fd13b]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/Target/X86/X86ISelLowering.cpp | 19 ++++++++++++++-----
- llvm/lib/Target/X86/X86InstrAVX512.td   |  3 ---
- 2 files changed, 14 insertions(+), 8 deletions(-)
-
-diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
-index 56690c3c555b..7e673a3163b7 100644
---- a/llvm/lib/Target/X86/X86ISelLowering.cpp
-+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
-@@ -23549,17 +23549,22 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
-   // Without AVX512DQ, we need to use a scalar type for v2i1/v4i1/v8i1 stores.
-   if (StoredVal.getValueType().isVector() &&
-       StoredVal.getValueType().getVectorElementType() == MVT::i1) {
--    assert(StoredVal.getValueType().getVectorNumElements() <= 8 &&
--           "Unexpected VT");
-+    unsigned NumElts = StoredVal.getValueType().getVectorNumElements();
-+    assert(NumElts <= 8 && "Unexpected VT");
-     assert(!St->isTruncatingStore() && "Expected non-truncating store");
-     assert(Subtarget.hasAVX512() && !Subtarget.hasDQI() &&
-            "Expected AVX512F without AVX512DQI");
- 
-+    // We must pad with zeros to ensure we store zeroes to any unused bits.
-     StoredVal = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
-                             DAG.getUNDEF(MVT::v16i1), StoredVal,
-                             DAG.getIntPtrConstant(0, dl));
-     StoredVal = DAG.getBitcast(MVT::i16, StoredVal);
-     StoredVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, StoredVal);
-+    // Make sure we store zeros in the extra bits.
-+    if (NumElts < 8)
-+      StoredVal = DAG.getZeroExtendInReg(StoredVal, dl,
-+                                         MVT::getIntegerVT(NumElts));
- 
-     return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
-                         St->getPointerInfo(), St->getOriginalAlign(),
-@@ -44133,17 +44138,21 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
-   if (VT == MVT::v1i1 && VT == StVT && Subtarget.hasAVX512() &&
-       StoredVal.getOpcode() == ISD::SCALAR_TO_VECTOR &&
-       StoredVal.getOperand(0).getValueType() == MVT::i8) {
--    return DAG.getStore(St->getChain(), dl, StoredVal.getOperand(0),
-+    SDValue Val = StoredVal.getOperand(0);
-+    // We must store zeros to the unused bits.
-+    Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1);
-+    return DAG.getStore(St->getChain(), dl, Val,
-                         St->getBasePtr(), St->getPointerInfo(),
-                         St->getOriginalAlign(),
-                         St->getMemOperand()->getFlags());
-   }
- 
-   // Widen v2i1/v4i1 stores to v8i1.
--  if ((VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
-+  if ((VT == MVT::v1i1 || VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
-       Subtarget.hasAVX512()) {
-     unsigned NumConcats = 8 / VT.getVectorNumElements();
--    SmallVector<SDValue, 4> Ops(NumConcats, DAG.getUNDEF(VT));
-+    // We must store zeros to the unused bits.
-+    SmallVector<SDValue, 4> Ops(NumConcats, DAG.getConstant(0, dl, VT));
-     Ops[0] = StoredVal;
-     StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
-     return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
-diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
-index a3ad0b1c8dd6..aa1ccec02f2a 100644
---- a/llvm/lib/Target/X86/X86InstrAVX512.td
-+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
-@@ -2871,9 +2871,6 @@ def : Pat<(i64 (bitconvert (v64i1 VK64:$src))),
- 
- // Load/store kreg
- let Predicates = [HasDQI] in {
--  def : Pat<(store VK1:$src, addr:$dst),
--            (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
--
-   def : Pat<(v1i1 (load addr:$src)),
-             (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK1)>;
-   def : Pat<(v2i1 (load addr:$src)),
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0001-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch

@@ -1,51 +0,0 @@
-From 3632f727dfd786a8eca50bd01219669bbe7b0df9 Mon Sep 17 00:00:00 2001
-From: haonanya <haonan.yang@intel.com>
-Date: Tue, 11 May 2021 11:13:02 +0800
-Subject: [PATCH 1/3] Remove __IMAGE_SUPPORT__ macro for SPIR since SPIR
- doesn't require image support
-
-Upstream-Status: Backport [Taken from opencl-clang patches, https://github.com/intel/opencl-clang/blob/ocl-open-120/patches/clang/0001-Remove-__IMAGE_SUPPORT__-macro-for-SPIR.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/Frontend/InitPreprocessor.cpp     | 3 ---
- clang/test/Preprocessor/predefined-macros.c | 2 --
- 2 files changed, 5 deletions(-)
-
-diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp
-index c64a912ce919..c60972c96e5d 100644
---- a/clang/lib/Frontend/InitPreprocessor.cpp
-+++ b/clang/lib/Frontend/InitPreprocessor.cpp
-@@ -1121,9 +1121,6 @@ static void InitializePredefinedMacros(const TargetInfo &TI,
-   // OpenCL definitions.
-   if (LangOpts.OpenCL) {
-     TI.getOpenCLFeatureDefines(LangOpts, Builder);
--
--    if (TI.getTriple().isSPIR())
--      Builder.defineMacro("__IMAGE_SUPPORT__");
-   }
- 
-   if (TI.hasInt128Type() && LangOpts.CPlusPlus && LangOpts.GNUMode) {
-diff --git a/clang/test/Preprocessor/predefined-macros.c b/clang/test/Preprocessor/predefined-macros.c
-index e406b9a70570..88606518c7de 100644
---- a/clang/test/Preprocessor/predefined-macros.c
-+++ b/clang/test/Preprocessor/predefined-macros.c
-@@ -188,14 +188,12 @@
- 
- // RUN: %clang_cc1 %s -E -dM -o - -x cl -triple spir-unknown-unknown \
- // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SPIR
--// CHECK-SPIR-DAG: #define __IMAGE_SUPPORT__ 1
- // CHECK-SPIR-DAG: #define __SPIR__ 1
- // CHECK-SPIR-DAG: #define __SPIR32__ 1
- // CHECK-SPIR-NOT: #define __SPIR64__ 1
- 
- // RUN: %clang_cc1 %s -E -dM -o - -x cl -triple spir64-unknown-unknown \
- // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SPIR64
--// CHECK-SPIR64-DAG: #define __IMAGE_SUPPORT__ 1
- // CHECK-SPIR64-DAG: #define __SPIR__ 1
- // CHECK-SPIR64-DAG: #define __SPIR64__ 1
- // CHECK-SPIR64-NOT: #define __SPIR32__ 1
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0002-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch

@@ -1,52 +0,0 @@
-From 06cf750d2ef892eaa4f0ff5d0a9e9e5c49697264 Mon Sep 17 00:00:00 2001
-From: Raphael Isemann <teemperor@gmail.com>
-Date: Thu, 1 Apr 2021 18:41:44 +0200
-Subject: [PATCH 2/3] Avoid calling ParseCommandLineOptions in BackendUtil if
- possible
-
-Calling `ParseCommandLineOptions` should only be called from `main` as the
-CommandLine setup code isn't thread-safe. As BackendUtil is part of the
-generic Clang FrontendAction logic, a process which has several threads executing
-Clang FrontendActions will randomly crash in the unsafe setup code.
-
-This patch avoids calling the function unless either the debug-pass option or
-limit-float-precision option is set. Without these two options set the
-`ParseCommandLineOptions` call doesn't do anything beside parsing
-the command line `clang` which doesn't set any options.
-
-See also D99652 where LLDB received a workaround for this crash.
-
-Reviewed By: JDevlieghere
-
-Differential Revision: https://reviews.llvm.org/D99740
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-120/patches/clang/0002-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/CodeGen/BackendUtil.cpp | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
-index 52bcd971dc8c..f9f891247530 100644
---- a/clang/lib/CodeGen/BackendUtil.cpp
-+++ b/clang/lib/CodeGen/BackendUtil.cpp
-@@ -850,7 +850,15 @@ static void setCommandLineOpts(const CodeGenOptions &CodeGenOpts) {
-     BackendArgs.push_back("-limit-float-precision");
-     BackendArgs.push_back(CodeGenOpts.LimitFloatPrecision.c_str());
-   }
-+  // Check for the default "clang" invocation that won't set any cl::opt values.
-+  // Skip trying to parse the command line invocation to avoid the issues
-+  // described below.
-+  if (BackendArgs.size() == 1)
-+    return;
-   BackendArgs.push_back(nullptr);
-+  // FIXME: The command line parser below is not thread-safe and shares a global
-+  // state, so this call might crash or overwrite the options of another Clang
-+  // instance in the same process.
-   llvm::cl::ParseCommandLineOptions(BackendArgs.size() - 1,
-                                     BackendArgs.data());
- }
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0003-Support-cl_ext_float_atomics.patch

@@ -1,344 +0,0 @@
-From f1a24eeb89342186c6c718e02dd394775620799f Mon Sep 17 00:00:00 2001
-From: haonanya <haonan.yang@intel.com>
-Date: Wed, 28 Jul 2021 14:20:08 +0800
-Subject: [PATCH 3/3] Support cl_ext_float_atomics
-
-Upstream-Status: Backport [Taken from opencl-clang patches; https://github.com/intel/opencl-clang/blob/ocl-open-120/patches/clang/0003-OpenCL-Support-cl_ext_float_atomics.patch]
-
-Signed-off-by: haonanya <haonan.yang@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- clang/lib/Headers/opencl-c-base.h     |  19 +++
- clang/lib/Headers/opencl-c.h          | 195 ++++++++++++++++++++++++++
- clang/test/Headers/opencl-c-header.cl |  72 ++++++++++
- 3 files changed, 286 insertions(+)
-
-diff --git a/clang/lib/Headers/opencl-c-base.h b/clang/lib/Headers/opencl-c-base.h
-index e8dcd70377e5..c8b6d36029ec 100644
---- a/clang/lib/Headers/opencl-c-base.h
-+++ b/clang/lib/Headers/opencl-c-base.h
-@@ -21,6 +21,25 @@
- #define cl_khr_subgroup_shuffle 1
- #define cl_khr_subgroup_shuffle_relative 1
- #define cl_khr_subgroup_clustered_reduce 1
-+#define cl_ext_float_atomics
-+#ifdef cl_khr_fp16
-+#define __opencl_c_ext_fp16_global_atomic_load_store 1
-+#define __opencl_c_ext_fp16_local_atomic_load_store 1
-+#define __opencl_c_ext_fp16_global_atomic_add 1
-+#define __opencl_c_ext_fp16_local_atomic_add 1
-+#define __opencl_c_ext_fp16_global_atomic_min_max 1
-+#define __opencl_c_ext_fp16_local_atomic_min_max 1
-+#endif
-+#ifdef __opencl_c_fp64
-+#define __opencl_c_ext_fp64_global_atomic_add 1
-+#define __opencl_c_ext_fp64_local_atomic_add 1
-+#define __opencl_c_ext_fp64_global_atomic_min_max 1
-+#define __opencl_c_ext_fp64_local_atomic_min_max 1
-+#endif
-+#define __opencl_c_ext_fp32_global_atomic_add 1
-+#define __opencl_c_ext_fp32_local_atomic_add 1
-+#define __opencl_c_ext_fp32_global_atomic_min_max 1
-+#define __opencl_c_ext_fp32_local_atomic_min_max 1
- #endif // defined(__SPIR__)
- #endif // (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
- 
-diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h
-index ab665628c8e1..6676da858d2a 100644
---- a/clang/lib/Headers/opencl-c.h
-+++ b/clang/lib/Headers/opencl-c.h
-@@ -13531,6 +13531,201 @@ intptr_t __ovld atomic_fetch_max_explicit(volatile atomic_intptr_t *object, uint
- intptr_t __ovld atomic_fetch_max_explicit(volatile atomic_intptr_t *object, uintptr_t opermax, memory_order minder, memory_scope scope);
- #endif
- 
-+#if defined(cl_ext_float_atomics)
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_max(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_min_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_max(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_min_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp32_local_atomic_min_max)
-+float __ovld atomic_fetch_min(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_max(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_min_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_max_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_min_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_max_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_global_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_max(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_min_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_max(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_min_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_global_atomic_min_max) ||                      \
-+    defined(__opencl_c_ext_fp64_local_atomic_min_max)
-+double __ovld atomic_fetch_min(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_max(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_min_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_max_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_min_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_max_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+
-+#if defined(__opencl_c_ext_fp32_global_atomic_add)
-+float __ovld atomic_fetch_add(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_sub(volatile __global atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_add_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile __global atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_local_atomic_add)
-+float __ovld atomic_fetch_add(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_sub(volatile __local atomic_float *object,
-+                              float operand);
-+float __ovld atomic_fetch_add_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile __local atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp32_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp32_local_atomic_add)
-+float __ovld atomic_fetch_add(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_sub(volatile atomic_float *object, float operand);
-+float __ovld atomic_fetch_add_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_sub_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order);
-+float __ovld atomic_fetch_add_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+float __ovld atomic_fetch_sub_explicit(volatile atomic_float *object,
-+                                       float operand, memory_order order,
-+                                       memory_scope scope);
-+#endif
-+
-+#if defined(__opencl_c_ext_fp64_global_atomic_add)
-+double __ovld atomic_fetch_add(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_sub(volatile __global atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_add_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile __global atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_local_atomic_add)
-+double __ovld atomic_fetch_add(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_sub(volatile __local atomic_double *object,
-+                               double operand);
-+double __ovld atomic_fetch_add_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile __local atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+#if defined(__opencl_c_ext_fp64_global_atomic_add) ||                          \
-+    defined(__opencl_c_ext_fp64_local_atomic_add)
-+double __ovld atomic_fetch_add(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_sub(volatile atomic_double *object, double operand);
-+double __ovld atomic_fetch_add_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_sub_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order);
-+double __ovld atomic_fetch_add_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+double __ovld atomic_fetch_sub_explicit(volatile atomic_double *object,
-+                                        double operand, memory_order order,
-+                                        memory_scope scope);
-+#endif
-+
-+#endif // cl_ext_float_atomics
-+
- // atomic_store()
- 
- void __ovld atomic_store(volatile atomic_int *object, int desired);
-diff --git a/clang/test/Headers/opencl-c-header.cl b/clang/test/Headers/opencl-c-header.cl
-index 13a3b62481ec..2c02d14f25c3 100644
---- a/clang/test/Headers/opencl-c-header.cl
-+++ b/clang/test/Headers/opencl-c-header.cl
-@@ -124,6 +124,36 @@ global atomic_int z = ATOMIC_VAR_INIT(99);
- #if cl_khr_subgroup_clustered_reduce != 1
- #error "Incorrectly defined cl_khr_subgroup_clustered_reduce"
- #endif
-+#if __opencl_c_ext_fp16_global_atomic_load_store != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_load_store"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_load_store != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_load_store"
-+#endif
-+#if __opencl_c_ext_fp16_global_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp32_global_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_global_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp32_local_atomic_add != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_local_atomic_add"
-+#endif
-+#if __opencl_c_ext_fp16_global_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_global_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp32_global_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_global_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp16_local_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp16_local_atomic_min_max"
-+#endif
-+#if __opencl_c_ext_fp32_local_atomic_min_max != 1
-+#error "Incorrectly defined __opencl_c_ext_fp32_local_atomic_min_max"
-+#endif
- 
- #else
- 
-@@ -148,6 +178,48 @@ global atomic_int z = ATOMIC_VAR_INIT(99);
- #ifdef cl_khr_subgroup_clustered_reduce
- #error "Incorrect cl_khr_subgroup_clustered_reduce define"
- #endif
-+#ifdef __opencl_c_ext_fp16_global_atomic_load_store
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_load_store defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_load_store
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_load_store defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp32_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_global_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp64_global_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp32_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_local_atomic_add
-+#error "Incorrectly __opencl_c_ext_fp64_local_atomic_add defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp16_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp32_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_global_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp64_global_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp16_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp16_local_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp32_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp32_local_atomic_min_max defined"
-+#endif
-+#ifdef __opencl_c_ext_fp64_local_atomic_min_max
-+#error "Incorrectly __opencl_c_ext_fp64_local_atomic_min_max defined"
-+#endif
- 
- #endif //(defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200)
- 
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch

@@ -1,67 +0,0 @@
-From 0c4ba4947d1630f2e13fc260399f0892b2c9b323 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 10:55:13 +0800
-Subject: [PATCH 1/2] This patch is needed for ISPC for Gen only
-
-1. Transformation of add to or is not safe for VC backend.
-2. bswap intrinsics is not supported in VC backend yet.
-
-Upstream-Status: Backport [Taken from ispc, https://github.com/ispc/ispc/blob/v1.16.1/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp  | 10 +++++++---
- .../lib/Transforms/InstCombine/InstCombineAndOrXor.cpp |  9 ++++++---
- 2 files changed, 13 insertions(+), 6 deletions(-)
-
-diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-index bacb8689892a..f3d0120db256 100644
---- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-@@ -15,6 +15,7 @@
- #include "llvm/ADT/APInt.h"
- #include "llvm/ADT/STLExtras.h"
- #include "llvm/ADT/SmallVector.h"
-+#include "llvm/ADT/Triple.h"
- #include "llvm/Analysis/InstructionSimplify.h"
- #include "llvm/Analysis/ValueTracking.h"
- #include "llvm/IR/Constant.h"
-@@ -1363,9 +1364,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
-     }
-   }
- 
--  // A+B --> A|B iff A and B have no bits set in common.
--  if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
--    return BinaryOperator::CreateOr(LHS, RHS);
-+  // Disable this transformation for ISPC SPIR-V
-+  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
-+    // A+B --> A|B iff A and B have no bits set in common.
-+    if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
-+      return BinaryOperator::CreateOr(LHS, RHS);
-+  }
- 
-   // add (select X 0 (sub n A)) A  -->  select X A n
-   {
-diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
-index 68c4156af2c4..b145b863ca84 100644
---- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
-+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
-@@ -2584,9 +2584,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
-   if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
-     return FoldedLogic;
- 
--  if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
--                                                  /*MatchBitReversals*/ false))
--    return BSwap;
-+  // Disable this transformation for ISPC SPIR-V
-+  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
-+    if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
-+                                                    /*MatchBitReversals*/ false))
-+      return BSwap;
-+  }
- 
-   if (Instruction *Funnel = matchFunnelShift(I, *this))
-     return Funnel;
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0005-ispc-12_0_fix_for_2111.patch

@@ -1,35 +0,0 @@
-From 913e07ea5acf2148e3748b45ddfe3fac3b2d051c Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 10:56:57 +0800
-Subject: [PATCH 2/2] This patch is a fix for #2111
-
-It ensures that shuffle is lowered for this particular case correctly.
-
-Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/9ab99f773fec7da4183495a3fdc655a797d3bea2]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
-index 6b816c710f98..3121b0e818ac 100644
---- a/llvm/lib/Target/X86/X86ISelLowering.cpp
-+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
-@@ -43192,9 +43192,10 @@ static SDValue combineHorizOpWithShuffle(SDNode *N, SelectionDAG &DAG,
-           ShuffleVectorSDNode::commuteMask(ShuffleMask1);
-         }
-         if ((Op00 == Op10) && (Op01 == Op11)) {
--          SmallVector<int, 4> ShuffleMask;
--          ShuffleMask.append(ShuffleMask0.begin(), ShuffleMask0.end());
--          ShuffleMask.append(ShuffleMask1.begin(), ShuffleMask1.end());
-+          const int Map[4] = {0, 2, 1, 3};
-+          SmallVector<int, 4> ShuffleMask(
-+            {Map[ShuffleMask0[0]], Map[ShuffleMask1[0]], Map[ShuffleMask0[1]],
-+             Map[ShuffleMask1[1]]});
-           SDLoc DL(N);
-           MVT ShufVT = VT.isFloatingPoint() ? MVT::v4f64 : MVT::v4i64;
-           SDValue Res = DAG.getNode(Opcode, DL, VT, Op00, Op01);
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-devtools/clang/llvm-project-source.bbappend

@@ -1,62 +0,0 @@
-FILESEXTRAPATHS:prepend:intel-x86-common := "${THISDIR}/files:"
-
-SPIRV10_SRCREV = "fe4d6b767363a1995ccbfca27f79efb10dcfe110"
-SPIRV11_SRCREV = "ca3a50e6e3193e399d26446d4f74a90e2a531f3a"
-
-SPIRV_SRCREV = "${@bb.utils.contains('LLVMVERSION', '10.0.1', '${SPIRV10_SRCREV}', '${SPIRV11_SRCREV}', d)}"
-
-SRC_URI_LLVM10_PATCHES = " \
-                   file://llvm10-0001-llvm-spirv-skip-building-tests.patch;patchdir=llvm/projects/llvm-spirv \
-                   file://llvm10-0002-Fix-building-in-tree-with-cmake-DLLVM_LINK_LLVM_DYLI.patch;patchdir=llvm/projects/llvm-spirv \
-                   file://llvm10-0003-Add-support-for-cl_ext_float_atomics-in-SPIRVWriter.patch;patchdir=llvm/projects/llvm-spirv \
-                   file://BasicBlockUtils-Add-metadata-fixing-in-SplitBlockPre.patch;patchdir=llvm \
-                   file://IndVarSimplify-Do-not-use-SCEV-expander-for-IVCount-.patch;patchdir=llvm \
-                   file://llvm10-0001-OpenCL-3.0-support.patch \
-                   file://llvm10-0002-Add-cl_khr_extended_subgroup-extensions.patch \
-                   file://llvm10-0003-Memory-leak-fix-for-Managed-Static-Mutex.patch \
-                   file://llvm10-0004-Remove-repo-name-in-LLVM-IR.patch \
-                   file://llvm10-0005-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch \
-                   file://llvm10-0006-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch \
-                   file://llvm10-0007-support-cl_ext_float_atomics.patch \
-                   file://llvm10-0008-ispc-10_0_9_0_fix_for_1767.patch \
-                   file://llvm10-0009-ispc-10_0_fix_for_1788.patch \
-                   file://llvm10-0010-ispc-10_0_fix_for_1793.patch \
-                   file://llvm10-0011-ispc-10_0_fix_for_1844.patch \
-                   file://llvm10-0012-ispc-10_0_i8_shuffle_avx512_i8_i16.patch \
-                   file://llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch \
-                   file://llvm10-0014-ispc-10_0_packed_load_store_avx512skx.patch \
-                   file://llvm10-0015-ispc-10_0_vXi1calling_avx512_i8_i16.patch \
-                   "
-
-SRC_URI_LLVM11_PATCHES = " \
-                   file://llvm11-0001-llvm-spirv-skip-building-tests.patch;patchdir=llvm/projects/llvm-spirv \
-                   file://llvm11-0002-Add-support-for-cl_ext_float_atomics-in-SPIRVWriter.patch;patchdir=llvm/projects/llvm-spirv \
-                   file://llvm11-0001-OpenCL-3.0-support.patch \
-                   file://llvm11-0002-Memory-leak-fix-for-Managed-Static-Mutex.patch \
-                   file://llvm11-0003-Remove-repo-name-in-LLVM-IR.patch \
-                   file://llvm11-0004-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch \
-                   file://llvm11-0005-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch \
-                   file://llvm11-0006-OpenCL-support-cl_ext_float_atomics.patch \
-                   file://llvm11-0007-ispc-11_0_11_1_disable-A-B-A-B-in-InstCombine.patch \
-                   file://llvm11-0008-ispc-11_0_11_1_packed_load_store_avx512.patch \
-                   "
-SRC_URI_LLVM12_PATCHES = " \
-                   file://llvm12-0001-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch \
-                   file://llvm12-0002-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch \
-                   file://llvm12-0003-Support-cl_ext_float_atomics.patch \
-                   file://llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch \
-                   file://llvm12-0005-ispc-12_0_fix_for_2111.patch \
-                   "
-
-
-SPIRV_LLVM10_SRC_URI = "git://github.com/KhronosGroup/SPIRV-LLVM-Translator.git;protocol=https;branch=llvm_release_100;destsuffix=git/llvm/projects/llvm-spirv;name=spirv"
-
-SPIRV_LLVM11_SRC_URI = "git://github.com/KhronosGroup/SPIRV-LLVM-Translator.git;protocol=https;branch=llvm_release_110;destsuffix=git/llvm/projects/llvm-spirv;name=spirv"
-
-
-
-SRC_URI:append:intel-x86-common = "${@bb.utils.contains('LLVMVERSION', '10.0.1', ' ${SPIRV_LLVM10_SRC_URI} ${SRC_URI_LLVM10_PATCHES} ', '', d)}"
-SRC_URI:append:intel-x86-common = "${@bb.utils.contains('LLVMVERSION', '11.1.0', ' ${SPIRV_LLVM11_SRC_URI} ${SRC_URI_LLVM11_PATCHES} ', '', d)}"
-SRC_URI:append:intel-x86-common = "${@bb.utils.contains('LLVMVERSION', '12.0.0', ' ${SRC_URI_LLVM12_PATCHES} ', '', d)}"
-
-SRCREV_spirv = "${@bb.utils.contains_any('LLVMVERSION', [ '13.0.0', '12.0.0' ], '', '${SPIRV_SRCREV}', d)}"

dynamic-layers/clang-layer/recipes-opencl/compute-runtime/intel-compute-runtime/0002-Build-not-able-to-locate-cpp_generation_tool.patch

@@ -1,34 +1,34 @@
-From 47ae5d13ad021076f5a79f245e33bcb228b0a0da Mon Sep 17 00:00:00 2001
+From 8c330d0cb5167612296801f0202b0de35e9ca88d Mon Sep 17 00:00:00 2001
 From: Dongwon Kim <dongwon.kim@intel.com>
 Date: Sat, 21 Aug 2021 16:09:39 -0700
-Subject: [PATCH] Build not able to locate cpp_generation_tool.
+Subject: [PATCH 2/5] Build not able to locate cpp_generation_tool.
 
 Upstream-Status: Inappropriate [oe specific]
 
 Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
 Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
 ---
- shared/source/built_ins/kernels/CMakeLists.txt | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
+ shared/source/built_ins/kernels/CMakeLists.txt | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
 
-diff --git a/shared/source/built_ins/kernels/CMakeLists.txt b/shared/source/built_ins/kernels/CMakeLists.txt
-index 929b981fe..57cd3d4b3 100644
---- a/shared/source/built_ins/kernels/CMakeLists.txt
-+++ b/shared/source/built_ins/kernels/CMakeLists.txt
-@@ -100,9 +100,9 @@ if(NOT NEO_DISABLE_BUILTINS_COMPILATION)
-       )
+Index: git/shared/source/built_ins/kernels/CMakeLists.txt
+===================================================================
+--- git.orig/shared/source/built_ins/kernels/CMakeLists.txt
++++ git/shared/source/built_ins/kernels/CMakeLists.txt
+@@ -122,9 +122,9 @@ function(compile_builtin core_type platf
+       endif()
        add_custom_command(
                           OUTPUT ${OUTPUT_FILE_CPP}
--                         COMMAND $<TARGET_FILE:cpp_generate_tool> --file ${BINARY_OUTPUT}.gen --output ${OUTPUT_FILE_CPP} --array ${mode}_${BASENAME} --platform ${family_name_with_type} --revision_id ${REVISION_ID}
-+                         COMMAND cpp_generate_tool --file ${BINARY_OUTPUT}.gen --output ${OUTPUT_FILE_CPP} --array ${mode}_${BASENAME} --platform ${family_name_with_type} --revision_id ${REVISION_ID}
+-                         COMMAND $<TARGET_FILE:cpp_generate_tool> --file ${BINARY_OUTPUT}.bin --output ${OUTPUT_FILE_CPP} --array ${mode}_${BASENAME} --device ${RELEASE_FILENAME}
++                         COMMAND cpp_generate_tool --file ${BINARY_OUTPUT}.bin --output ${OUTPUT_FILE_CPP} --array ${mode}_${BASENAME} --device ${RELEASE_FILENAME}
                           WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
 -                         DEPENDS ${OUTPUT_FILES_BINARIES} $<TARGET_FILE:cpp_generate_tool>
 +                         DEPENDS ${OUTPUT_FILES_BINARIES} cpp_generate_tool
        )
-     endforeach()
-     set(BUILTINS_COMMANDS ${BUILTINS_COMMANDS} PARENT_SCOPE)
-@@ -144,9 +144,9 @@ if(NOT NEO_DISABLE_BUILTINS_COMPILATION)
-     )
+       list(APPEND BUILTINS_COMMANDS "${OUTPUT_FILE_CPP}")
+     else()
+@@ -176,9 +176,9 @@ function(generate_cpp_spirv builtin)
+     endif()
      add_custom_command(
                         OUTPUT ${OUTPUT_FILE_CPP}
 -                       COMMAND $<TARGET_FILE:cpp_generate_tool> --file ${GENERATED_SPV_INPUT} --output ${OUTPUT_FILE_CPP} --array ${BASENAME}
@@ -37,8 +37,5 @@ index 929b981fe..57cd3d4b3 100644
 -                       DEPENDS ${GENERATED_SPV_INPUT} $<TARGET_FILE:cpp_generate_tool>
 +                       DEPENDS ${GENERATED_SPV_INPUT} cpp_generate_tool
      )
-   endfunction()
- 
--- 
-2.32.0
-
+     set(OUTPUT_LIST_CPP_FILES ${OUTPUT_LIST_CPP_FILES} ${OUTPUT_FILE_CPP} PARENT_SCOPE)
+   else()

dynamic-layers/clang-layer/recipes-opencl/compute-runtime/intel-compute-runtime/0003-external-ocloc.patch

@@ -0,0 +1,38 @@
+From 0006db5f55a9f08bd3452558a53704cd3bbb790f Mon Sep 17 00:00:00 2001
+From: Dongwon Kim <dongwon.kim@intel.com>
+Date: Wed, 2 Mar 2022 15:52:45 -0800
+Subject: [PATCH 3/5] external ocloc
+
+Upstream-Status: Inappropriate
+
+Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
+---
+ cmake/ocloc_cmd_prefix.cmake | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+Index: git/cmake/ocloc_cmd_prefix.cmake
+===================================================================
+--- git.orig/cmake/ocloc_cmd_prefix.cmake
++++ git/cmake/ocloc_cmd_prefix.cmake
+@@ -4,13 +4,15 @@
+ # SPDX-License-Identifier: MIT
+ #
+ 
+-if(WIN32)
+-  set(ocloc_cmd_prefix ocloc)
+-else()
+-  if(DEFINED NEO__IGC_LIBRARY_PATH)
+-    set(ocloc_cmd_prefix ${CMAKE_COMMAND} -E env "LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${NEO__IGC_LIBRARY_PATH}:$<TARGET_FILE_DIR:ocloc_lib>" $<TARGET_FILE:ocloc>)
++if(NOT DEFINED ocloc_cmd_prefix)
++  if(WIN32)
++    set(ocloc_cmd_prefix ocloc)
+   else()
+-    set(ocloc_cmd_prefix ${CMAKE_COMMAND} -E env "LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:$<TARGET_FILE_DIR:ocloc_lib>" $<TARGET_FILE:ocloc>)
++    if(DEFINED NEO__IGC_LIBRARY_PATH)
++      set(ocloc_cmd_prefix LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${NEO__IGC_LIBRARY_PATH}:$<TARGET_FILE_DIR:ocloc_lib> $<TARGET_FILE:ocloc>)
++    else()
++      set(ocloc_cmd_prefix LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:$<TARGET_FILE_DIR:ocloc_lib> $<TARGET_FILE:ocloc>)
++    endif()
+   endif()
+ endif()
+ 

dynamic-layers/clang-layer/recipes-opencl/compute-runtime/intel-compute-runtime_25.13.33276.16.bb

@@ -4,25 +4,22 @@ is an open source project to converge Intel's development efforts \
 on OpenCL(TM) compute stacks supporting the GEN graphics hardware \
 architecture."
 
-LICENSE = "MIT"
-LIC_FILES_CHKSUM = "file://LICENSE.md;md5=983b0c493ea3dc3c21a90ff743bf90e4 \
-                    file://third_party/opencl_headers/LICENSE;md5=dcefc90f4c3c689ec0c2489064e7273b"
+LICENSE = "MIT & Apache-2.0"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eca6ec6997e18db166db7109cdbe611c \
+                    file://third_party/opencl_headers/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57"
 
-SRC_URI = "git://github.com/intel/compute-runtime.git;protocol=https \
-          "
+SRC_URI = "git://github.com/intel/compute-runtime.git;protocol=https;branch=releases/25.13 \
+           file://0002-Build-not-able-to-locate-cpp_generation_tool.patch \
+           file://0003-external-ocloc.patch \
+           "
 
-SRC_URI:append:class-target = "file://allow-to-find-cpp-generation-tool.patch"
+SRCREV = "a9961bdfaa07250fd52ff930bf8f31fb4e3b7799"
 
-SRCREV = "3269e719a3ee7bcd97c50ec2cfe78fc8674adec0"
-
-S = "${WORKDIR}/git"
-
-DEPENDS += " intel-graphics-compiler gmmlib"
-DEPENDS:append:class-target = " intel-compute-runtime-native libva"
+DEPENDS += " intel-graphics-compiler gmmlib libva qemu-native"
 
 RDEPENDS:${PN} += " intel-graphics-compiler gmmlib"
 
-inherit cmake pkgconfig
+inherit cmake pkgconfig qemu
 
 COMPATIBLE_HOST = '(x86_64).*-linux'
 COMPATIBLE_HOST:libc-musl = "null"
@@ -35,18 +32,23 @@ EXTRA_OECMAKE = " \
                  -DNEO_DISABLE_LD_LLD=ON \
                  -DNEO_DISABLE_LD_GOLD=ON \
                  "
-EXTRA_OECMAKE:append:class-native = " -DNEO_DISABLE_BUILTINS_COMPILATION=ON"
 
 EXTRA_OECMAKE:append:class-target = " \
-                                     -Dcloc_cmd_prefix=ocloc \
-                                    "
+                                     -Docloc_cmd_prefix=ocloc \
+                                     -DCMAKE_CROSSCOMPILING_EMULATOR=${WORKDIR}/qemuwrapper \
+                                     "
 
 PACKAGECONFIG ??= ""
 PACKAGECONFIG[levelzero] = "-DBUILD_WITH_L0=ON, -DBUILD_WITH_L0=OFF, level-zero"
 
-do_install:append:class-native() {
-    install -d ${D}${bindir}
-    install ${B}/bin/cpp_generate_tool ${D}${bindir}/
+do_configure:prepend:class-target () {
+    # Write out a qemu wrapper that will be used by cmake.
+    qemu_binary="${@qemu_wrapper_cmdline(d, d.getVar('STAGING_DIR_HOST'), [d.expand('${B}/bin'),d.expand('${STAGING_DIR_HOST}${libdir}'),d.expand('${STAGING_DIR_HOST}${base_libdir}')])}"
+    cat > ${WORKDIR}/qemuwrapper << EOF
+#!/bin/sh
+$qemu_binary "\$@"
+EOF
+    chmod +x ${WORKDIR}/qemuwrapper
 }
 
 FILES:${PN} += " \
@@ -56,6 +58,4 @@ FILES:${PN} += " \
 
 FILES:${PN}-dev = "${includedir}"
 
-BBCLASSEXTEND = "native nativesdk"
-
 UPSTREAM_CHECK_GITTAGREGEX = "(?P<pver>\d+(\.\d+)+)"

dynamic-layers/clang-layer/recipes-opencl/igc/files/0001-BiF-CMakeLists.txt-remove-opt-from-DEPENDS.patch

@@ -0,0 +1,32 @@
+From 1b98a931c3bf8daccc48cd618335ff35e3d382da Mon Sep 17 00:00:00 2001
+From: Anuj Mittal <anuj.mittal@intel.com>
+Date: Tue, 12 Oct 2021 23:46:42 +0800
+Subject: [PATCH] BiF/CMakeLists.txt: remove opt from DEPENDS
+
+Otherwise it starts failing with:
+
+| ninja: error: 'IGC/VectorCompiler/lib/BiF/opt', needed by 'IGC/VectorCompiler/lib/BiF/VCBiFPrintfOCL32.opt.bc', missing and no known rule to make it
+
+We don't need to explicitly make sure opt is built when
+using prebuilt binaries.
+
+Upstream-Status: Inappropriate
+
+Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
+---
+ IGC/VectorCompiler/lib/BiF/cmake/Functions.cmake | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+Index: git/IGC/VectorCompiler/lib/BiF/cmake/Functions.cmake
+===================================================================
+--- git.orig/IGC/VectorCompiler/lib/BiF/cmake/Functions.cmake
++++ git/IGC/VectorCompiler/lib/BiF/cmake/Functions.cmake
+@@ -121,7 +121,7 @@ function(vc_build_bif RES_FILE CMCL_SRC_
+     COMMENT "vc_build_bif: Translating CMCL builtins:  ${BIF_CLANG_BC_NAME_FINAL} -> ${BIF_OPT_BC_NAME}"
+     COMMAND CMCLTranslatorTool ${OPT_OPAQUE_ARG} -o ${BIF_CMCL_BC_PATH} ${BIF_CLANG_BC_PATH_FINAL}
+     COMMAND ${LLVM_OPT_EXE} ${OPT_OPAQUE_ARG} --O2 -o ${BIF_OPT_BC_PATH} ${BIF_CMCL_BC_PATH}
+-    DEPENDS CMCLTranslatorTool ${LLVM_OPT_EXE} ${OPT_BC_DEPENDS})
++    DEPENDS CMCLTranslatorTool ${BIF_CLANG_BC_PATH_FINAL})
+ 
+   add_custom_target(${TARGET_NAME}
+     DEPENDS ${BIF_OPT_BC_PATH}

dynamic-layers/clang-layer/recipes-opencl/igc/files/0001-Build-not-able-to-locate-BiFManager-bin.patch

@@ -0,0 +1,27 @@
+From 048512728eea53b3772a3f80ac9743bfc462487e Mon Sep 17 00:00:00 2001
+From: Yogesh Tyagi <yogesh.tyagi@intel.com>
+Date: Thu, 2 Jan 2025 15:59:27 +0530
+Subject: [PATCH] Build not able to locate BiFManager-bin
+
+Upstream-Status: Inappropriate [oe specific]
+
+Signed-off-by: Yogesh Tyagi <yogesh.tyagi@intel.com>
+---
+ IGC/BiFModule/CMakeLists.txt | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+Index: git/IGC/BiFModule/CMakeLists.txt
+===================================================================
+--- git.orig/IGC/BiFModule/CMakeLists.txt
++++ git/IGC/BiFModule/CMakeLists.txt
+@@ -655,8 +655,8 @@ set(IGC_BUILD__PROJ__BiFModuleCache_OCL
+ 
+ add_custom_command(
+     OUTPUT "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.h" "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bifbc"
+-    COMMAND $<TARGET_FILE:BiFManager-bin> "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_32.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_64.bc" "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bifbc" "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.h"
+-    DEPENDS "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_32.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_64.bc"$<TARGET_FILE:BiFManager-bin>
++    COMMAND BiFManager-bin "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_32.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_64.bc" "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bifbc" "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.h"
++    DEPENDS "${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_32.bc" "${IGC_BUILD__BIF_DIR}/IGCsize_t_64.bc" BiFManager-bin
+     COMMENT "BiF: ${IGC_BUILD__BIF_DIR}/OCLBiFImpl.bc: Spliting output .bc."
+     COMMAND_EXPAND_LISTS
+ )

dynamic-layers/clang-layer/recipes-opencl/igc/files/0001-external-SPIRV-Tools-change-path-to-tools-and-header.patch

@@ -0,0 +1,30 @@
+From 251e2854dd206ebf66e5908d3277e4585fe2a63b Mon Sep 17 00:00:00 2001
+From: Anuj Mittal <anuj.mittal@intel.com>
+Date: Mon, 9 Jan 2023 11:43:05 +0800
+Subject: [PATCH] external/SPIRV-Tools: change path to tools and headers
+
+We clone the SPIRV headers and tools in a different directory to ensure
+file path substitutions take place.
+
+Upstream-Status: Inappropriate
+
+Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
+---
+ external/SPIRV-Tools/CMakeLists.txt | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+Index: git/external/SPIRV-Tools/CMakeLists.txt
+===================================================================
+--- git.orig/external/SPIRV-Tools/CMakeLists.txt
++++ git/external/SPIRV-Tools/CMakeLists.txt
+@@ -45,8 +45,8 @@ else() #By default use build from source
+  message(STATUS "[SPIRV-Tools] : Building from source")
+  message(STATUS "[SPIRV-Tools] : Current source dir: ${CMAKE_CURRENT_SOURCE_DIR}")
+ 
+- set(SPIRV-Headers_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../SPIRV-Headers") # used in subdirectory
+- set(SPIRV-Tools_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../SPIRV-Tools")
++ set(SPIRV-Headers_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../SPIRV-Headers") # used in subdirectory
++ set(SPIRV-Tools_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../SPIRV-Tools")
+ 
+  set(SPIRV-Tools_OUTPUT_DIR "${IGC_OPTION__OUTPUT_DIR}/external/SPIRV-Tools/build")
+  set(IGC_BUILD__SPIRV-Headers_DIR "${SPIRV-Headers_SOURCE_DIR}")

dynamic-layers/clang-layer/recipes-opencl/igc/files/0001-fix-tblgen.patch

@@ -0,0 +1,23 @@
+From 1641dc87b2ed6b6b87b2cef824e4d66da65b0b30 Mon Sep 17 00:00:00 2001
+From: Anuj Mittal <anuj.mittal@intel.com>
+Date: Thu, 19 May 2022 22:50:09 +0800
+Subject: [PATCH] fix tblgen
+
+Upstream-Status: Inappropriate [OE specific]
+---
+ IGC/cmake/igc_llvm.cmake | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/IGC/cmake/igc_llvm.cmake b/IGC/cmake/igc_llvm.cmake
+index b708cc904..fe4668890 100644
+--- a/IGC/cmake/igc_llvm.cmake
++++ b/IGC/cmake/igc_llvm.cmake
+@@ -53,7 +53,7 @@ else()
+   set(LLVM_OPT_EXE "opt" CACHE STRING "")
+ 
+   set(LLVM_TABLEGEN_EXE "llvm-tblgen")
+-  if(CMAKE_CROSSCOMPILING)
++  if(TRUE)
+     if(DEFINED LLVM_TABLEGEN)
+       set(LLVM_TABLEGEN_EXE ${LLVM_TABLEGEN})
+     else()

dynamic-layers/clang-layer/recipes-opencl/igc/files/0001-llvm_deps.cmake-don-t-copy-header-file-when-building.patch

@@ -1,35 +0,0 @@
-From 3d99559779d628704568879a2ee51e968e66d005 Mon Sep 17 00:00:00 2001
-From: Anuj Mittal <anuj.mittal@intel.com>
-Date: Tue, 5 Oct 2021 00:11:26 +0800
-Subject: [PATCH] llvm_deps.cmake: don't copy header file when building
-
-We build in pre-built mode and this header shouldn't be copied in
-that case.
-
-Upstream-Status: Pending
-
-Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
----
- external/llvm/llvm_deps.cmake | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/external/llvm/llvm_deps.cmake b/external/llvm/llvm_deps.cmake
-index 425d3766f..e43804f77 100644
---- a/external/llvm/llvm_deps.cmake
-+++ b/external/llvm/llvm_deps.cmake
-@@ -46,9 +46,9 @@ if(IGC_OPTION__LLVM_LLD)
-   include(llvm_lld_source_hook)
-   if(NOT EXISTS "${IGC_LLVM_WORKSPACE_SRC}/libunwind/include/mach-o" AND ${IGC_OPTION__LLVM_PREFERRED_VERSION} GREATER_EQUAL "12.0.0")
-     # Need to copy one header from unwind package for LLD (only for building from sources)
--    file(MAKE_DIRECTORY ${IGC_LLVM_WORKSPACE_SRC}/libunwind/include/mach-o)
--    file(COPY ${DEFAULT_IGC_LLVM_SOURCES_DIR}/libunwind/include/mach-o/compact_unwind_encoding.h
--         DESTINATION ${IGC_LLVM_WORKSPACE_SRC}/libunwind/include/mach-o/)
-+    #file(MAKE_DIRECTORY ${IGC_LLVM_WORKSPACE_SRC}/libunwind/include/mach-o)
-+    #file(COPY ${DEFAULT_IGC_LLVM_SOURCES_DIR}/libunwind/include/mach-o/compact_unwind_encoding.h
-+    #     DESTINATION ${IGC_LLVM_WORKSPACE_SRC}/libunwind/include/mach-o/)
-   endif()
- endif()
- 
--- 
-2.32.0
-

dynamic-layers/clang-layer/recipes-opencl/igc/files/0003-Improve-Reproducibility-for-src-package.patch

@@ -1,7 +1,7 @@
-From c2b7f30dd56568482b1b7c2f22bafdf68736fc88 Mon Sep 17 00:00:00 2001
+From ca136c04d4ac60e3febc8ea2b9c4d4736365a424 Mon Sep 17 00:00:00 2001
 From: Lee Chee Yang <chee.yang.lee@intel.com>
 Date: Wed, 2 Sep 2020 08:28:35 +0800
-Subject: [PATCH 3/5] Improve Reproducibility for src package
+Subject: [PATCH] Improve Reproducibility for src package
 
 Improve reproducibility for intel-graphics-compiler-src package.
 needs to pass build path as environment variable to the build.
@@ -13,11 +13,11 @@ Signed-off-by: Lee Chee Yang <chee.yang.lee@intel.com>
  visa/CMakeLists.txt | 7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)
 
-diff --git a/visa/CMakeLists.txt b/visa/CMakeLists.txt
-index 65dbb4934..8cd607a69 100644
---- a/visa/CMakeLists.txt
-+++ b/visa/CMakeLists.txt
-@@ -123,8 +123,11 @@ endif()
+Index: git/visa/CMakeLists.txt
+===================================================================
+--- git.orig/visa/CMakeLists.txt
++++ git/visa/CMakeLists.txt
+@@ -135,8 +135,11 @@ endif()
  set(bison_output_file ${CMAKE_CURRENT_BINARY_DIR}/CISA.tab.cpp)
  set(flex_output_file ${CMAKE_CURRENT_BINARY_DIR}/lex.CISA.cpp)
  
@@ -31,6 +31,3 @@ index 65dbb4934..8cd607a69 100644
  ADD_FLEX_BISON_DEPENDENCY(CISAScanner CISAParser)
  set(CISAScanner_dependencies)
  
--- 
-2.20.1
-

dynamic-layers/clang-layer/recipes-opencl/igc/files/0004-find-external-llvm-tblgen.patch

@@ -1,30 +0,0 @@
-From c9fe51ec555fadd098cfc98804ce91b1cf3029d4 Mon Sep 17 00:00:00 2001
-From: Dongwon Kim <dongwon.kim@intel.com>
-Date: Thu, 19 Aug 2021 08:28:03 -0700
-Subject: [PATCH 4/5] find external llvm-tblgen
-
-Upstream-Status: Pending
-Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
----
- IGC/cmake/igc_llvm.cmake | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/IGC/cmake/igc_llvm.cmake b/IGC/cmake/igc_llvm.cmake
-index 541793f21..bc82922b1 100644
---- a/IGC/cmake/igc_llvm.cmake
-+++ b/IGC/cmake/igc_llvm.cmake
-@@ -24,7 +24,10 @@ set(CMAKE_MODULE_PATH
-   ${CMAKE_MODULE_PATH}
-   )
- 
--set(LLVM_TABLEGEN_EXE "llvm-tblgen")
-+find_program(LLVM_TABLEGEN_EXE "llvm-tblgen")
-+if(LLVM_TABLEGEN_EXE-NOTFOUND)
-+  message(FATAL_ERROR "[VC] llvm-tblgen is not found")
-+endif()
- 
- include(AddLLVM)
- include(TableGen)
--- 
-2.20.1
-

dynamic-layers/clang-layer/recipes-opencl/igc/intel-graphics-compiler_1.0.8744.bb

@@ -1,57 +0,0 @@
-SUMMARY = "The Intel(R) Graphics Compiler for OpenCL(TM)"
-DESCRIPTION = "The Intel(R) Graphics Compiler for OpenCL(TM) is an \
-llvm based compiler for OpenCL(TM) targeting Intel Gen graphics \
-hardware architecture."
-
-LICENSE = "MIT & BSD-3-Clause"
-LIC_FILES_CHKSUM = "file://IGC/BiFModule/Implementation/ExternalLibraries/libclc/LICENSE.TXT;md5=311cfc1a5b54bab8ed34a0b5fba4373e \
-                    file://IGC/Compiler/LegalizationPass.cpp;beginline=1;endline=23;md5=4a985f2545dd5a846e205b1e60a51cd9 \
-                    file://NOTICES.txt;md5=db621145dfb627436bc90ad600386801"
-
-SRC_URI = "git://github.com/intel/intel-graphics-compiler.git;protocol=https;name=igc \
-           git://github.com/intel/vc-intrinsics.git;protocol=https;destsuffix=git/vc-intrinsics;name=vc \
-           file://0001-llvm_deps.cmake-don-t-copy-header-file-when-building.patch \
-           file://0003-Improve-Reproducibility-for-src-package.patch \
-           file://0004-find-external-llvm-tblgen.patch \
-           "
-
-SRCREV_igc = "3ba8dde8c414a0e47df58b1bba12a64f8ba2089e"
-SRCREV_vc = "e5ad7e02aa4aa21a3cd7b3e5d1f3ec9b95f58872"
-
-# Used to replace with relative path in reproducibility patch
-export B
-
-S = "${WORKDIR}/git"
-
-inherit cmake
-
-CXXFLAGS:append = " -Wno-error=nonnull"
-
-COMPATIBLE_HOST = '(x86_64).*-linux'
-COMPATIBLE_HOST:libc-musl = "null"
-
-DEPENDS += " flex-native bison-native clang opencl-clang"
-DEPENDS:append:class-target = " clang-cross-x86_64 intel-graphics-compiler-native"
-
-RDEPENDS:${PN} += "opencl-clang"
-
-EXTRA_OECMAKE = " \
-                  -DIGC_OPTION__LLVM_PREFERRED_VERSION=${LLVMVERSION} \
-                  -DPYTHON_EXECUTABLE=${HOSTTOOLS_DIR}/python3 \
-                  -DVC_INTRINSICS_SRC="${S}/vc-intrinsics" \
-                  -DIGC_OPTION__LLVM_MODE=Prebuilds \
-                  -DIGC_BUILD__VC_ENABLED=OFF \
-                  "
-
-do_install:append:class-native () {
-    install -d ${D}${bindir}
-    install ${B}/IGC/Release/elf_packager ${D}${bindir}/
-}
-
-BBCLASSEXTEND = "native nativesdk"
-
-UPSTREAM_CHECK_GITTAGREGEX = "^igc-(?P<pver>(?!19\..*)\d+(\.\d+)+)$"
-
-FILES:${PN} += " \
-                 ${libdir}/igc/NOTICES.txt \
-                 "

dynamic-layers/clang-layer/recipes-opencl/igc/intel-graphics-compiler_2.10.10.bb

@@ -0,0 +1,78 @@
+SUMMARY = "The Intel(R) Graphics Compiler for OpenCL(TM)"
+DESCRIPTION = "The Intel(R) Graphics Compiler for OpenCL(TM) is an \
+llvm based compiler for OpenCL(TM) targeting Intel Gen graphics \
+hardware architecture."
+
+LICENSE = "MIT & Apache-2.0"
+LIC_FILES_CHKSUM = "file://IGC/BiFModule/Implementation/ExternalLibraries/libclc/LICENSE.TXT;md5=311cfc1a5b54bab8ed34a0b5fba4373e \
+                    file://LICENSE.md;md5=488d74376edf2765f6e78d271543dde3 \
+                    file://NOTICES.txt;md5=b81a52411c84df3419f20bad4d755880"
+
+SRC_URI = "git://github.com/intel/intel-graphics-compiler.git;protocol=https;name=igc;branch=releases/2.10.x \
+           git://github.com/intel/vc-intrinsics.git;protocol=https;destsuffix=${BB_GIT_DEFAULT_DESTSUFFIX}/vc-intrinsics;name=vc;nobranch=1 \
+           git://github.com/KhronosGroup/SPIRV-Tools.git;protocol=https;destsuffix=${BB_GIT_DEFAULT_DESTSUFFIX}/SPIRV-Tools;name=spirv-tools;branch=main \
+           git://github.com/KhronosGroup/SPIRV-Headers.git;protocol=https;destsuffix=${BB_GIT_DEFAULT_DESTSUFFIX}/SPIRV-Headers;name=spirv-headers;branch=main \
+           file://0003-Improve-Reproducibility-for-src-package.patch \
+           file://0001-BiF-CMakeLists.txt-remove-opt-from-DEPENDS.patch \
+           file://0001-external-SPIRV-Tools-change-path-to-tools-and-header.patch \
+           file://0001-Build-not-able-to-locate-BiFManager-bin.patch \
+           "
+
+SRC_URI:append:class-native = " file://0001-fix-tblgen.patch"
+
+SRCREV_igc = "83925314d4fc32b017fcbfcd73e0667ba833fb8f"
+SRCREV_vc = "9d255266e1df8f1dc5d11e1fbb03213acfaa4fc7"
+SRCREV_spirv-tools = "f289d047f49fb60488301ec62bafab85573668cc"
+SRCREV_spirv-headers = "0e710677989b4326ac974fd80c5308191ed80965"
+
+SRCREV_FORMAT = "igc_vc_spirv-tools_spirv-headers"
+
+# Used to replace with relative path in reproducibility patch
+export B
+
+inherit cmake pkgconfig qemu python3native
+
+CXXFLAGS:append = " -Wno-error=nonnull"
+
+COMPATIBLE_HOST = '(x86_64).*-linux'
+COMPATIBLE_HOST:libc-musl = "null"
+
+DEPENDS += " flex-native bison-native clang clang-cross-x86_64 opencl-clang qemu-native python3-mako-native \
+             python3-pyyaml-native \
+           "
+
+RDEPENDS:${PN} += "opencl-clang"
+
+PACKAGECONFIG ??= "vc"
+PACKAGECONFIG[vc] = "-DIGC_BUILD__VC_ENABLED=ON -DIGC_OPTION__LINK_KHRONOS_SPIRV_TRANSLATOR=ON -DIGC_OPTION__SPIRV_TRANSLATOR_MODE=Prebuilds,-DIGC_BUILD__VC_ENABLED=OFF,"
+
+EXTRA_OECMAKE = " \
+                  -DIGC_OPTION__LLVM_PREFERRED_VERSION=${LLVMVERSION} \
+                  -DVC_INTRINSICS_SRC="${S}/vc-intrinsics" \
+                  -DIGC_OPTION__LLVM_MODE=Prebuilds \
+                  -DLLVM_TABLEGEN=${STAGING_BINDIR_NATIVE}/llvm-tblgen \
+                  -DLLVM_LINK_EXE=${STAGING_BINDIR_NATIVE}/llvm-link \
+                  -DCLANG_EXE=${STAGING_BINDIR_NATIVE}/clang \
+                  -DCMAKE_CROSSCOMPILING_EMULATOR=${WORKDIR}/qemuwrapper \
+                  -DCMAKE_POLICY_VERSION_MINIMUM=3.5 \
+                  "
+
+do_configure:prepend:class-target () {
+    # Write out a qemu wrapper that will be used by cmake.
+    qemu_binary="${@qemu_wrapper_cmdline(d, d.getVar('STAGING_DIR_HOST'), [d.expand('${STAGING_DIR_HOST}${libdir}'),d.expand('${STAGING_DIR_HOST}${base_libdir}')])}"
+    cat > ${WORKDIR}/qemuwrapper << EOF
+#!/bin/sh
+$qemu_binary "\$@"
+EOF
+    chmod +x ${WORKDIR}/qemuwrapper
+}
+
+
+UPSTREAM_CHECK_GITTAGREGEX = "^v(?P<pver>\d+(\.\d+)+)$"
+
+FILES:${PN} += " \
+                 ${libdir}/igc2/NOTICES.txt \
+                 "
+
+# libigc.so contains buildpaths
+INSANE_SKIP:${PN} += "buildpaths"

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/files/0001-Building-in-tree-with-LLVM-10.0-with-the-LLVM_LINK_L.patch

@@ -1,35 +0,0 @@
-From 7fc05c52dd91902fa324a7aac9b90715cfca4717 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Wed, 15 Apr 2020 17:55:32 +0800
-Subject: [PATCH] Building in-tree with LLVM 10.0 with the LLVM_LINK_LLVM_DYLIB
-
-Failed to link with the LLVMSPIRVLib library.
-
-Add an explicit dependency to force the correct build order and linking.
-
-Reference:
-https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/a6d4ccf082858e63e139ca06c02a071c343d2657
-
-Upstream-Status: Submitted [https://github.com/intel/opencl-clang/pull/118]
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- CMakeLists.txt | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index 51c140d..b8b514e 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -208,7 +208,7 @@ link_directories(
- 
- set(OPENCL_CLANG_LINK_LIBS ${CMAKE_DL_LIBS})
- 
--if(NOT LLVMSPIRVLib IN_LIST LLVM_AVAILABLE_LIBS)
-+if(NOT LLVMSPIRVLib IN_LIST LLVM_AVAILABLE_LIBS OR (USE_PREBUILT_LLVM AND LLVM_LINK_LLVM_DYLIB))
-   # SPIRV-LLVM-Translator is not included into LLVM as a component.
-   # So, we need to list it here explicitly as an external library
-   list(APPEND OPENCL_CLANG_LINK_LIBS LLVMSPIRVLib)
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/files/0001-cl_headers-CMakeLists.txt-use-clang-from-native-sysr.patch

@@ -0,0 +1,49 @@
+From 5aea653e611b59c70e529a1bd71885a509831557 Mon Sep 17 00:00:00 2001
+From: Anuj Mittal <anuj.mittal@intel.com>
+Date: Tue, 1 Aug 2023 11:15:31 +0800
+Subject: [PATCH] cl_headers/CMakeLists.txt: use clang from native sysroot
+
+Allow clang to be found in target sysroot for target builds and dont try
+to compile cross binaries, we do that ourselves.
+
+Upstream-Status: Inappropriate [oe-specific]
+Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
+---
+ CMakeLists.txt            | 8 ++++----
+ cl_headers/CMakeLists.txt | 2 +-
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index 5864009..60ba39e 100644
+--- a/CMakeLists.txt
++++ b/CMakeLists.txt
+@@ -35,10 +35,10 @@ set(CMAKE_MODULE_PATH
+ 
+ include(CMakeFunctions)
+ 
+-if(CMAKE_CROSSCOMPILING AND OPENCL_CLANG_BUILD_EXTERNAL)
+-  include(CrossCompile)
+-  llvm_create_cross_target(${PROJECT_NAME} NATIVE "" Release)
+-endif()
++#if(CMAKE_CROSSCOMPILING AND OPENCL_CLANG_BUILD_EXTERNAL)
++#  include(CrossCompile)
++#  llvm_create_cross_target(${PROJECT_NAME} NATIVE "" Release)
++#endif()
+ 
+ if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR)
+     set(USE_PREBUILT_LLVM ON)
+diff --git a/cl_headers/CMakeLists.txt b/cl_headers/CMakeLists.txt
+index 16cabb7..4423536 100644
+--- a/cl_headers/CMakeLists.txt
++++ b/cl_headers/CMakeLists.txt
+@@ -1,6 +1,6 @@
+ set(CL_HEADERS_LIB cl_headers)
+ if(USE_PREBUILT_LLVM)
+-    find_program(CLANG_COMMAND clang PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH)
++    find_program(CLANG_COMMAND clang PATHS ${LLVM_TOOLS_BINARY_DIR})
+ else()
+     set(CLANG_COMMAND $<TARGET_FILE:clang>)
+ endif()
+-- 
+2.37.3
+

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/files/0001-don-t-redefine-LLVM_TABLEGEN_EXE.patch

@@ -1,32 +0,0 @@
-From f3ef79a6301bab0b3a447f07ceb94c39a95009df Mon Sep 17 00:00:00 2001
-From: Anuj Mittal <anuj.mittal@intel.com>
-Date: Thu, 2 Apr 2020 08:59:20 +0800
-Subject: [PATCH] don't redefine LLVM_TABLEGEN_EXE
-
-Use the value that has been passed by the user.
-
-Upstream-Status: Submitted
-Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
----
- CMakeLists.txt | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index 6893e97..941b0ae 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -137,7 +137,10 @@ endif(NOT USE_PREBUILT_LLVM)
- set (COMPILE_OPTIONS_TD  opencl_clang_options.td)
- set (COMPILE_OPTIONS_INC opencl_clang_options.inc)
- 
--set(LLVM_TABLEGEN_EXE "llvm-tblgen")
-+if(NOT DEFINED LLVM_TABLEGEN_EXE)
-+  set(LLVM_TABLEGEN_EXE "llvm-tblgen")
-+endif()
-+
- set(LLVM_TARGET_DEFINITIONS ${COMPILE_OPTIONS_TD})
- if(USE_PREBUILT_LLVM)
-   set(TABLEGEN_ADDITIONAL -I ${LLVM_INCLUDE_DIRS})
--- 
-2.25.1
-

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/files/0002-Request-native-clang-only-when-cross-compiling-464.patch

@@ -0,0 +1,60 @@
+From 43c806ef321b1f677a49d28c89fb7ffecf539c2d Mon Sep 17 00:00:00 2001
+From: Tim Creech <timothy.m.creech@intel.com>
+Date: Wed, 28 Jun 2023 03:45:51 -0400
+Subject: [PATCH 2/2] Request native clang only when cross-compiling (#464)
+
+* Request native clang only when cross-compiling
+
+LLVM_USE_HOST_TOOLS may be set if LLVM is configured with
+LLVM_OPTIMIZED_TABLEGEN, which does not necessarily indicate
+cross-compilation or that clang will only execute on the target.
+
+By checking that CMAKE_CROSSCOMPILING is set, we ensure that we only
+build/use clang again if necessary for host execution.
+
+* fixup: CMAKE_CROSSCOMPILING implies LLVM_USE_HOST_TOOLS
+
+Co-authored-by: Wenju He <wenju.he@intel.com>
+
+* fixup: also use CMAKE_CROSSCOMPILING in top-level CMakeLists.txt
+
+---------
+
+Co-authored-by: Wenju He <wenju.he@intel.com>
+
+Upstream-Status: Backport [https://github.com/intel/opencl-clang/commit/53843eee13cfb2357919ee02714a43bef1af0f86]
+Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
+---
+ CMakeLists.txt            | 2 +-
+ cl_headers/CMakeLists.txt | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index e772de9..5864009 100644
+--- a/CMakeLists.txt
++++ b/CMakeLists.txt
+@@ -35,7 +35,7 @@ set(CMAKE_MODULE_PATH
+ 
+ include(CMakeFunctions)
+ 
+-if(LLVM_USE_HOST_TOOLS AND OPENCL_CLANG_BUILD_EXTERNAL)
++if(CMAKE_CROSSCOMPILING AND OPENCL_CLANG_BUILD_EXTERNAL)
+   include(CrossCompile)
+   llvm_create_cross_target(${PROJECT_NAME} NATIVE "" Release)
+ endif()
+diff --git a/cl_headers/CMakeLists.txt b/cl_headers/CMakeLists.txt
+index 18296c2..16cabb7 100644
+--- a/cl_headers/CMakeLists.txt
++++ b/cl_headers/CMakeLists.txt
+@@ -4,7 +4,7 @@ if(USE_PREBUILT_LLVM)
+ else()
+     set(CLANG_COMMAND $<TARGET_FILE:clang>)
+ endif()
+-if(LLVM_USE_HOST_TOOLS AND NOT OPENCL_CLANG_BUILD_EXTERNAL)
++if(CMAKE_CROSSCOMPILING AND NOT OPENCL_CLANG_BUILD_EXTERNAL)
+   build_native_tool(clang CLANG_COMMAND)
+ endif()
+ 
+-- 
+2.37.3
+

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/files/0002-make-sure-only-static-libraries-linked-for-native-bu.patch

@@ -1,42 +0,0 @@
-From b29e00e6fe428a031cf577dfb703cf13eff837f6 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Wed, 15 Apr 2020 18:05:14 +0800
-Subject: [PATCH 2/2] make sure only static libraries linked for native build
-
-LINK_COMPONENTS=all isn't working for static libs for out of tree builds. Use
-LLVM_AVAILABLE_LIBS instead. Reported:
-
-https://github.com/intel/opencl-clang/issues/114
-
-Upstream-Status: Pending
-
-Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- CMakeLists.txt | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index 8707487..ad2dbda 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -218,7 +218,7 @@ add_subdirectory(cl_headers)
- 
- set(LLVM_REQUIRES_EH ON)
- 
--if(USE_PREBUILT_LLVM OR CLANG_LINK_CLANG_DYLIB)
-+if(false)
-   list(APPEND OPENCL_CLANG_LINK_LIBS clang-cpp)
- else()
-   list(APPEND OPENCL_CLANG_LINK_LIBS
-@@ -266,6 +266,7 @@ add_llvm_library(${TARGET_NAME} SHARED
-     all
-   LINK_LIBS
-     ${OPENCL_CLANG_LINK_LIBS}
-+    ${LLVM_AVAILABLE_LIBS}
-   )
- 
- # Configure resource file on Windows
--- 
-2.17.1
-

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/opencl-clang.inc

@@ -6,8 +6,9 @@ LICENSE = "NCSA"
 LIC_FILES_CHKSUM = "file://LICENSE;md5=e8a15bf1416762a09ece07e44c79118c"
 
 SRC_URI = "git://github.com/intel/opencl-clang.git;branch=${BRANCH};protocol=https \
+           file://0002-Request-native-clang-only-when-cross-compiling-464.patch \
+           file://0001-cl_headers-CMakeLists.txt-use-clang-from-native-sysr.patch \
            "
-S = "${WORKDIR}/git"
 
 inherit cmake
 DEPENDS += "clang"
@@ -16,9 +17,18 @@ DEPENDS:append:class-target = " opencl-clang-native"
 COMPATIBLE_HOST = '(x86_64).*-linux'
 COMPATIBLE_HOST:libc-musl = "null"
 
+DEPENDS += " spirv-llvm-translator"
+
+EXTRA_OECMAKE += "\
+                  -DLLVM_TABLEGEN_EXE=${STAGING_BINDIR_NATIVE}/llvm-tblgen \
+                  -DCMAKE_SKIP_RPATH=TRUE \
+                  -DPREFERRED_LLVM_VERSION=${LLVMVERSION} \
+                  -DCMAKE_POLICY_VERSION_MINIMUM=3.5 \
+                  "
+
 do_install:append:class-native() {
         install -d ${D}${bindir}
-        install -m 0755 ${B}/linux_linker/linux_resource_linker ${D}${bindir}/
+        install -m 0755 ${B}/bin/linux_resource_linker ${D}${bindir}/
 }
 
 BBCLASSEXTEND = "native nativesdk"

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/opencl-clang_10.0.0.bb

@@ -1,15 +0,0 @@
-require opencl-clang.inc
-
-SRC_URI:append = " file://0001-don-t-redefine-LLVM_TABLEGEN_EXE.patch \
-           file://0001-Building-in-tree-with-LLVM-10.0-with-the-LLVM_LINK_L.patch \
-           "
-SRC_URI:append:class-native = " file://0002-make-sure-only-static-libraries-linked-for-native-bu.patch"
-
-BRANCH = "ocl-open-100"
-
-SRCREV = "c8cd72e32b6abc18ce6da71c357ea45ba78b52f0"
-
-EXTRA_OECMAKE += "\
-                  -DLLVM_TABLEGEN_EXE=${STAGING_BINDIR_NATIVE}/llvm-tblgen \
-                  -DCMAKE_SKIP_RPATH=TRUE \
-                  "

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/opencl-clang_11.0.0.bb

@@ -1,15 +0,0 @@
-require opencl-clang.inc
-
-SRC_URI:append = " file://0001-don-t-redefine-LLVM_TABLEGEN_EXE.patch \
-           "
-SRC_URI:append:class-native = " file://0002-make-sure-only-static-libraries-linked-for-native-bu.patch"
-
-SRCREV = "c67648d41df00ea8ee9d701d17299b86f86f0321"
-
-BRANCH = "ocl-open-110"
-
-EXTRA_OECMAKE += "\
-                  -DLLVM_TABLEGEN_EXE=${STAGING_BINDIR_NATIVE}/llvm-tblgen \
-                  -DCMAKE_SKIP_RPATH=TRUE \
-                  -DPREFERRED_LLVM_VERSION="11.1.0" \
-                  "

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/opencl-clang_12.0.0.bb

@@ -1,12 +0,0 @@
-require opencl-clang.inc
-
-SRCREV = "8fc6b059248dc6c9c40c7cbe5fedcc6ebb951983"
-
-DEPENDS += " spirv-llvm-translator"
-
-BRANCH = "ocl-open-120"
-
-EXTRA_OECMAKE += "\
-                  -DCMAKE_SKIP_RPATH=TRUE \
-                  -DPREFERRED_LLVM_VERSION="12.0.0" \
-                  "

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/opencl-clang_13.0.0.bb

@@ -1,15 +0,0 @@
-require opencl-clang.inc
-
-SRC_URI:append = " file://0001-don-t-redefine-LLVM_TABLEGEN_EXE.patch \
-           "
-SRCREV = "0f36f940b25b8e7661cfaf8a7c11fdbb7d853223"
-
-BRANCH = "ocl-open-130"
-
-DEPENDS += " spirv-llvm-translator"
-
-EXTRA_OECMAKE += "\
-                  -DLLVM_TABLEGEN_EXE=${STAGING_BINDIR_NATIVE}/llvm-tblgen \
-                  -DCMAKE_SKIP_RPATH=TRUE \
-                  -DPREFERRED_LLVM_VERSION=${LLVMVERSION} \
-                  "

dynamic-layers/clang-layer/recipes-opencl/opencl-clang/opencl-clang_15.0.0.bb

@@ -0,0 +1,5 @@
+require opencl-clang.inc
+
+SRCREV = "60fd799cc58755c16d951f9ebfde6d0f9b8554dd"
+
+BRANCH = "ocl-open-150"

dynamic-layers/clang-layer/recipes-opencl/vc-intrinsics/vc-intrinsics_1.0.bb

@@ -1,24 +0,0 @@
-SUMMARY = "VC Intrinsics"
-DESCRIPTION = "VC Intrinsics project contains a set of new intrinsics on \
-top of core LLVM IR instructions that represent SIMD semantics of a program \
-targeting GPU"
-
-LICENSE = "MIT"
-LIC_FILES_CHKSUM = "file://Readme.md;beginline=1;endline=7;md5=3b2db19c3b0877bb312b7adbcb815adc"
-
-SRC_URI = "git://github.com/intel/vc-intrinsics.git;protocol=https; \
-          "
-SRCREV = "a2f2f10dc61c8161c57cf33ed606c8e3ccf3a921"
-
-S = "${WORKDIR}/git"
-
-inherit cmake
-
-COMPATIBLE_HOST = '(x86_64).*-linux'
-COMPATIBLE_HOST:libc-musl = "null"
-
-DEPENDS += "  clang"
-
-EXTRA_OECMAKE = "-DLLVM_DIR=${STAGING_LIBDIR}"
-
-BBCLASSEXTEND = "native nativesdk"

dynamic-layers/meta-python/recipes-opencv/dldt/openvino-model-optimizer_2021.4.1.bb

@@ -1,35 +0,0 @@
-SUMMARY = "OpenVINO Model Optimzer"
-DESCRIPTION = "Model Optimizer is a cross-platform command-line tool that \
-facilitates the transition between the training and deployment \
-environment, performs static model analysis, and adjusts deep \
-learning models for optimal execution on end-point target devices."
-HOMEPAGE = "https://01.org/openvinotoolkit"
-
-SRC_URI = "git://github.com/openvinotoolkit/openvino.git;protocol=https;branch=releases/2021/4;lfs=0 \
-           "
-SRCREV = "c2bfbf29fbc44f9a3c8403d77da5be7e45cbbb4f"
-
-LICENSE = "Apache-2.0"
-LIC_FILES_CHKSUM = "file://LICENSE;md5=86d3f3a95c324c9479bd8986968f4327"
-
-CVE_PRODUCT = "intel:openvino"
-
-S = "${WORKDIR}/git"
-
-do_install() {
-        mkdir -p ${D}${datadir}/openvino/model-optimizer
-        cp -r model-optimizer ${D}${datadir}/openvino/
-}
-
-RDEPENDS:${PN} += " \
-                    python3-numpy \
-                    python3-protobuf \
-                    python3-defusedxml \
-                    python3-networkx \
-                    python3-test-generator \
-                    python3-requests \
-                    python3-urllib3 \
-                    bash \
-                    "
-
-FILES:${PN} += "${datadir}/openvino"

dynamic-layers/openembedded-layer/recipes-bsp/amt/files/0001-LMS-fix-build-issue-with-gcc-15.patch

@@ -0,0 +1,32 @@
+From 439af27f7641185933d7810b6c4eb17086438df3 Mon Sep 17 00:00:00 2001
+From: Yogesh Tyagi <yogesh.tyagi@intel.com>
+Date: Mon, 19 May 2025 17:50:40 +0530
+Subject: [PATCH] LMS : fix build issue with gcc 15
+
+include cstdint header to resolve the below error with gcc 15
+
+| In file included from /lms/2406.0.0.0/git/MEIClient/src/MEICommand.cpp:11:
+| /lms/2406.0.0.0/git/MEIClient/Include/MEICommand.h:40:54: error: 'uint8_t' was not declared in this scope
+
+Upstream-Status: Submitted [https://github.com/intel/lms/pull/23]
+
+Signed-off-by: Yogesh Tyagi <yogesh.tyagi@intel.com>
+---
+ MEIClient/Include/MEICommand.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/MEIClient/Include/MEICommand.h b/MEIClient/Include/MEICommand.h
+index 6192d26..5332e44 100644
+--- a/MEIClient/Include/MEICommand.h
++++ b/MEIClient/Include/MEICommand.h
+@@ -12,6 +12,7 @@
+ #define __MEI_COMMAND_H__
+ #include "heci.h"
+ #include "MEIClientException.h"
++#include <cstdint>
+ #include <memory>
+ #include <vector>
+ 
+-- 
+2.43.0
+

dynamic-layers/openembedded-layer/recipes-bsp/amt/files/0001-cmake-Bump-required-CMake-version-to-3.5-to-allow-bu.patch

@@ -0,0 +1,39 @@
+From e1f6129390706044112496b6f10baee5b604b4c8 Mon Sep 17 00:00:00 2001
+From: Yogesh Tyagi <yogesh.tyagi@intel.com>
+Date: Wed, 23 Jul 2025 23:48:41 +0800
+Subject: [PATCH] cmake: Bump required CMake version to 3.5 to allow builds
+ with CMake 4+
+
+This enables builds with CMake 4+, fixing:
+
+    CMake Error at CMakeLists.txt:1 (cmake_minimum_required):
+      Compatibility with CMake < 3.5 has been removed from CMake.
+
+      Update the VERSION argument <min> value.  Or, use the <min>...<max> syntax
+      to tell CMake that the project requires at least <min> but has been
+      updated to work with policies introduced by <max> or earlier.
+
+      Or, add -DCMAKE_POLICY_VERSION_MINIMUM=3.5 to try configuring anyway.
+
+Upstream-Status: Inappropriate
+
+Signed-off-by: Yogesh Tyagi <yogesh.tyagi@intel.com>
+---
+ CIM_Framework/openwsman/CMakeLists.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/CIM_Framework/openwsman/CMakeLists.txt b/CIM_Framework/openwsman/CMakeLists.txt
+index 6e54c66..e2ffa5f 100644
+--- a/CIM_Framework/openwsman/CMakeLists.txt
++++ b/CIM_Framework/openwsman/CMakeLists.txt
+@@ -6,7 +6,7 @@ PROJECT(openwsman)
+
+ # 2.6 minimum because of CMP0005 (escaping defines)
+ # 2.8.12 minimum because CMake 3.19.7 says so
+-cmake_minimum_required(VERSION 2.8.12)
++cmake_minimum_required(VERSION 3.5)
+
+ include(CTest)
+ enable_testing()
+--
+2.37.3

dynamic-layers/openembedded-layer/recipes-bsp/amt/lms_2406.0.0.0.bb

@@ -10,30 +10,33 @@ COMPATIBLE_HOST = '(i.86|x86_64).*-linux'
 
 COMPATIBLE_HOST:libc-musl = "null"
 
-inherit cmake systemd features_check
+inherit cmake systemd features_check python3native
 
-DEPENDS = "metee ace xerces-c libnl libxml2 glib-2.0 glib-2.0-native pkgconfig-native"
-
-EXTRA_OECMAKE += "-DPYTHON_EXECUTABLE=${HOSTTOOLS_DIR}/python3"
+DEPENDS = "metee ace xerces-c libnl libxml2 glib-2.0 glib-2.0-native pkgconfig-native python3-packaging-native"
 
 # Enable either connman or networkmanager or none but not both.
 PACKAGECONFIG ??= "connman"
 PACKAGECONFIG[connman]        = "-DNETWORK_CN=ON, -DNETWORK_CN=OFF, connman"
 PACKAGECONFIG[networkmanager] = "-DNETWORK_NM=ON, -DNETWORK_NM=OFF, networkmanager"
 
-REQUIRED_DISTRO_FEATURES= "systemd"
+REQUIRED_DISTRO_FEATURES = "systemd"
+
+EXTRA_OECMAKE += " \
+                  -DCMAKE_POLICY_VERSION_MINIMUM=3.5 \
+                  "
 
 FILES:${PN} += "${datadir}/dbus-1/system-services/*.service"
 
-S = "${WORKDIR}/git"
-
 SYSTEMD_SERVICE:${PN} = "lms.service"
 
-SRC_URI = "git://github.com/intel/lms.git \
+SRC_URI = "git://github.com/intel/lms.git;branch=master;protocol=https \
+           file://0001-LMS-fix-build-issue-with-gcc-15.patch \
+           file://0001-cmake-Bump-required-CMake-version-to-3.5-to-allow-bu.patch \
            "
-SRCREV = "6ef4440c40783aad218efa6df8768d8c99380c2b"
+SRCREV = "388f115b2aeb3ea11499971c65f828daefd32c47"
 
 do_install:append() {
+    install -d ${D}${sysconfdir}/lms
     install -d ${D}${systemd_system_unitdir}
     install -m 0644 ${B}/UNS/lms.service ${D}${systemd_system_unitdir}
     install -d ${D}${sysconfdir}/udev/rules.d
@@ -42,5 +45,4 @@ do_install:append() {
 
 RDEPENDS:${PN} += "ace"
 
-# This CVE is for Lan Management System software and not this lms.
-CVE_CHECK_WHITELIST += "CVE-2018-1000535"
+CVE_STATUS[CVE-2018-1000535] = "cpe-incorrect: This CVE is for a different LMS - Lan Management System."

dynamic-layers/openembedded-layer/recipes-bsp/thermald/thermald_2.5.8.bb

@@ -7,14 +7,15 @@ compensation using available cooling methods."
 HOMEPAGE = "https://github.com/01org/thermal_daemon"
 
 DEPENDS = "dbus dbus-glib dbus-glib-native libxml2 glib-2.0 glib-2.0-native upower libevdev"
-LICENSE = "GPLv2"
+DEPENDS += "autoconf-archive-native"
+
+LICENSE = "GPL-2.0-only"
 LIC_FILES_CHKSUM = "file://COPYING;md5=ea8831610e926e2e469075b52bf08848"
 
-SRC_URI = "git://github.com/intel/thermal_daemon/ \
+SRC_URI = "git://github.com/intel/thermal_daemon/;branch=master;protocol=https \
            "
 
-SRCREV = "dddba484b23562d421cdaf1703dabc602e1968e7"
-S = "${WORKDIR}/git"
+SRCREV = "df3b9ab0ffe780c4fbad7750987eff76f659cfd5"
 
 inherit pkgconfig autotools systemd gtk-doc
 
@@ -28,7 +29,7 @@ EXTRA_OECONF = " \
                  --with-systemdsystemunitdir=${systemd_system_unitdir} \
                  "
 
-FILES:${PN} += "${datadir}/dbus-1/system-services/*.service"
+FILES:${PN} += "${datadir}/dbus-1"
 
 SYSTEMD_SERVICE:${PN} = "thermald.service"
 

dynamic-layers/openembedded-layer/recipes-core/ispc/ispc/0001-Add-print-function-to-print-test-run-status-in-ptest.patch

@@ -0,0 +1,53 @@
+From deccc0c69c2c8759c52885be8bdda54d3cee481c Mon Sep 17 00:00:00 2001
+From: Yogesh Tyagi <yogesh.tyagi@intel.com>
+Date: Sun, 11 Dec 2022 22:34:15 +0800
+Subject: [PATCH] Add print function to print test run status in ptest format
+
+Upstream-Status: Inappropriate [OE ptest specific]
+
+Signed-off-by: Yogesh Tyagi <yogesh.tyagi@intel.com>
+---
+ run_tests.py | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/run_tests.py b/run_tests.py
+index 1cd796dd..e3ffd1ab 100755
+--- a/run_tests.py
++++ b/run_tests.py
+@@ -327,6 +327,9 @@ def run_test(testname, host, target):
+     else:
+         ispc_exe_rel = add_prefix(host.ispc_cmd, host, target)
+ 
++    # to reslove the error '.rodata' can not be used when making a PIE object
++    ispc_exe_rel = ispc_exe_rel + " --pic"
++
+     # is this a test to make sure an error is issued?
+     want_error = (filename.find("tests_errors") != -1)
+     if want_error == True:
+@@ -795,6 +798,17 @@ def check_compiler_exists(compiler_exe):
+             return
+     error("missing the required compiler: %s \n" % compiler_exe, 1)
+ 
++def print_test_run_status(results):
++    for fstatus in results:
++       if (fstatus[1]  ==  Status.Success):
++          print( "%s: %s" % ("PASS", fstatus[0]))
++       elif (fstatus[1] ==  Status.Compfail):
++          print( "%s: %s" % ("FAIL", fstatus[0]))
++       elif (fstatus[1] ==  Status.Runfail):
++          print( "%s: %s" % ("FAIL", fstatus[0]))
++       elif (fstatus[1] ==  Status.Skip):
++          print( "%s: %s" % ("SKIP", fstatus[0]))
++
+ def print_result(status, results, s, run_tests_log, csv):
+     title = StatusStr[status]
+     file_list = [fname for fname, fstatus in results if status == fstatus]
+@@ -938,6 +952,8 @@ def run_tests(options1, args, print_version):
+         pass_rate = -1
+     print_debug("PASSRATE (%d/%d) = %d%% \n\n" % (len(run_succeed_files), total_tests_executed, pass_rate), s, run_tests_log)
+ 
++    print_test_run_status(results)
++
+     for status in Status:
+         print_result(status, results, s, run_tests_log, options.csv)
+     fails = [status != Status.Compfail and status != Status.Runfail for _, status in results]

dynamic-layers/openembedded-layer/recipes-core/ispc/ispc/0001-Fix-QA-Issues.patch

@@ -0,0 +1,36 @@
+From 7beff95c11071170eb27b6fa7d0cc77588caee8e Mon Sep 17 00:00:00 2001
+From: Yogesh Tyagi <yogesh.tyagi@intel.com>
+Date: Tue, 26 Jul 2022 15:25:10 +0800
+Subject: [PATCH] Fix QA Issues
+
+Stop ispc from inserting host file path in generated headers which leads to reproducibility problems.
+
+Upstream-Status: Inappropriate [OE build specific]
+
+Signed-off-by: Yogesh Tyagi <yogesh.tyagi@intel.com>
+---
+ src/module.cpp | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/module.cpp b/src/module.cpp
+index e2084d2e..e2626865 100644
+--- a/src/module.cpp
++++ b/src/module.cpp
+@@ -2555,7 +2555,7 @@ bool Module::writeHeader(const char *fn) {
+         perror("fopen");
+         return false;
+     }
+-    fprintf(f, "//\n// %s\n// (Header automatically generated by the ispc compiler.)\n", fn);
++    fprintf(f, "//\n// \n// (Header automatically generated by the ispc compiler.)\n");
+     fprintf(f, "// DO NOT EDIT THIS FILE.\n//\n\n");
+ 
+     // Create a nice guard string from the filename, turning any
+@@ -2677,7 +2677,7 @@ bool Module::writeDispatchHeader(DispatchHeaderInfo *DHI) {
+     FILE *f = DHI->file;
+ 
+     if (DHI->EmitFrontMatter) {
+-        fprintf(f, "//\n// %s\n// (Header automatically generated by the ispc compiler.)\n", DHI->fn);
++        fprintf(f, "//\n// \n// (Header automatically generated by the ispc compiler.)\n");
+         fprintf(f, "// DO NOT EDIT THIS FILE.\n//\n\n");
+     }
+     // Create a nice guard string from the filename, turning any

dynamic-layers/openembedded-layer/recipes-core/ispc/ispc/0002-cmake-don-t-build-for-32-bit-targets.patch

@@ -1,6 +1,6 @@
-From 3f3f81bde7d9d80921515ed0bf7fe36e69319bc4 Mon Sep 17 00:00:00 2001
+From 16a2c22339287122d2c25d8bb33a5a51b4e6ee51 Mon Sep 17 00:00:00 2001
 From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Wed, 30 Jun 2021 13:47:41 +0800
+Date: Thu, 24 Feb 2022 20:01:11 +0530
 Subject: [PATCH] cmake: don't build for 32-bit targets
 
 Error log:
@@ -16,14 +16,14 @@ Upstream-Status: Inappropriate
 
 Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
 ---
- cmake/GenerateBuiltins.cmake | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
+ cmake/GenerateBuiltins.cmake | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/cmake/GenerateBuiltins.cmake b/cmake/GenerateBuiltins.cmake
-index 15a74788..db30f809 100644
+index f84494ed..d90cb1ec 100644
 --- a/cmake/GenerateBuiltins.cmake
 +++ b/cmake/GenerateBuiltins.cmake
-@@ -249,7 +249,7 @@ function(builtin_to_cpp bit os_name arch supported_archs supported_oses resultFi
+@@ -253,7 +253,7 @@ function(builtin_to_cpp bit os_name arch supported_archs supported_oses resultFi
              #   In this case headers will be installed in /usr/arm-linux-gnueabihf/include and will not be picked up
              #   by clang by default. So the following line adds such path explicitly. If this path doesn't exist and
              #   the headers can be found in other locations, this should not be a problem.
@@ -32,7 +32,7 @@ index 15a74788..db30f809 100644
          endif()
      endif()
  
-@@ -331,7 +331,7 @@ function (generate_target_builtins resultList)
+@@ -339,7 +339,7 @@ function (generate_target_builtins resultList)
      set(regular_targets ${ARGN})
      list(FILTER regular_targets EXCLUDE REGEX wasm)
      foreach (ispc_target ${regular_targets})
@@ -41,24 +41,12 @@ index 15a74788..db30f809 100644
              foreach (os_name ${TARGET_OS_LIST_FOR_LL})
                  target_ll_to_cpp(target-${ispc_target} ${bit} ${os_name} output${os_name}${bit})
                  list(APPEND tmpList ${output${os_name}${bit}})
-@@ -392,7 +392,7 @@ function (generate_common_builtins resultList)
+@@ -405,7 +405,7 @@ function (generate_common_builtins resultList)
      endif()
  
      message (STATUS "ISPC will be built with support of ${supported_oses} for ${supported_archs}")
 -    foreach (bit 32 64)
 +    foreach (bit 64)
          foreach (os_name "windows" "linux" "freebsd" "macos" "android" "ios" "ps4" "web")
-             foreach (arch "x86" "arm" "wasm32")
+             foreach (arch "x86" "arm" "wasm")
                  builtin_to_cpp(${bit} ${os_name} ${arch} "${supported_archs}" "${supported_oses}" res${bit}${os_name}${arch})
-@@ -405,7 +405,7 @@ function (generate_common_builtins resultList)
-         endforeach()
-     endforeach()
-     if (GENX_ENABLED)
--        foreach (bit 32 64)
-+        foreach (bit 64)
-             builtin_genx_to_cpp(${bit} res_genx_${bit})
-             list(APPEND tmpList ${res_genx_${bit}} )
-             if(MSVC)
--- 
-2.17.1
-