mirror of
git://git.yoctoproject.org/meta-intel
synced 2026-01-01 13:58:05 +00:00
Enable cyclictest: - test execute cyclictest, retrieve the maximum latency captured inside log and compare it to the target latency - cyclictest arguments based on public cyclictest arguments used for intel corei7 https://www.osadl.org/Latency-plot-of-system-in-rack-9-slot.qa-latencyplot-r9s5.0.html?shadow=1 - set default target latency based on 24 us (captured from public cyclictest execution) multiple by 1.2 (buffer) - enable user defined target latency by configuring 'RTKERNEL_TARGET_LATENCY' as bitbake config example, inside local.conf: RTKERNEL_TARGET_LATENCY = "25" Signed-off-by: Yeoh Ee Peng <ee.peng.yeoh@intel.com> Signed-off-by: Anuj Mittal <anuj.mittal@intel.com> |
||
|---|---|---|
| .. | ||
| cases | ||
| files/dldt-inference-engine | ||
| miutils | ||